Commit Graph

3198 Commits (e76f287e737429c61cb021397ea0fcba0bdfea04)

Author SHA1 Message Date
Laszlo Nagy e76f287e73 ad9081_fmca_ebz:vcu128: Initial version
* 4Txs / 4Rxs per MxFE
 * Tx I/Q Rate: 250 MSPS
 * Rx I/Q Rate: 250 MSPS
 * DAC JESD204B: Mode 9, L=4, M=8, N=N'=16
 * ADC JESD204B: Mode 10, L=4, M=8, N=N'=16
 * DAC-Side JESD204B Lane Rate: 10Gbps
 * ADC-Side JESD204B Lane Rate: 10Gbps
2021-11-19 18:08:16 +02:00
Laszlo Nagy 88b5c2d6db projects/common/vcu128: Initial VCU128 support 2021-11-19 18:08:16 +02:00
Laszlo Nagy e00def31d0 ad9081_fmca_ebz: versal: Remove external gt_reset logic 2021-11-19 14:01:48 +02:00
Laszlo Nagy 0b9631f1f7 ad9081_fmca_ebz: versal: Rename nets 2021-11-19 14:01:48 +02:00
Laszlo Nagy ca6248ba88 ad9081_fmca_ebz/common/versal_transceiver.tcl: Reset also PLL 2021-11-19 14:01:48 +02:00
Laszlo Nagy 731ed0a7a5 ad9081_fmca_ebz/vck190: Updated to hierarchical versal transceiver
Vivado cannot nest multiple block designs than two layers. This makes
replication of designs difficult.

Create a hierarchy around the Versal transceiver that includes also the
converters, this type of interface would match the util_adxcvr
interface.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-19 14:01:48 +02:00
Laszlo Nagy 1d951cfbae ad9081_fmca_ebz/vck190: Change default profile to 2 lanes 2021-11-19 14:01:48 +02:00
sergiu arpadi 81c7d7475d ad463x: Fix readme 2021-11-17 16:48:59 +02:00
Laszlo Nagy 5795cf6720 ad9213_dual_ebz: Readme.md : Remove incorrect product page 2021-11-15 13:59:26 +02:00
Laszlo Nagy daba543797 ad9082_fmca_ebz: Readme.md: Remove AD9081 from parts 2021-11-15 13:59:26 +02:00
Laszlo Nagy fe9afd4392 ad9208_dual_ebz: Readme.md: Remove invalid product page
Product page on analog.com does not exists
2021-11-15 13:59:26 +02:00
Laszlo Nagy 2386abb89c ad_quadmxfe1_ebz : Add readme file 2021-11-12 14:08:56 +02:00
stefan.raus adad6c930d ad9081_fmca_ebz_qsys.tcl: Add RX_LANE_RATE and TX_LANE_RATE parameters
For ad9081/a10soc project, the RX_LANE_RATE and TX_LANE_RATE were computed
from SAMPLE_RATE. Remove SAMPLE_RATE and add RX_LANE_RATE and TX_LANE_RATE
as parameters. Update also computation examples from comments.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-11-12 13:04:57 +02:00
Laszlo Nagy fe58a5fb47 adrv9009zu11eg/adrv2crr_fmcomms8: Add clock buffers for core clocks
The IBUFGDS primitive is deprecated in UltraScale devices.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-11 17:33:10 +02:00
Laszlo Nagy 1cd866445e ad_quadmxfe1_ebz: Initial version
Parametrizable project for the QUAD-MxFE platform ADQUADMXFE1EBZ,
ADQUADMXFE2EBZ, ADQUADMXFE3EBZ

Default mode set to:
  TX JESD204C MODE 11, M=16, L=4
  RX JESD204C MODE 4, M=8, L=2

For 204C 64B66B mode as physical layer the Xilinx Phy is uesd.
2021-11-10 14:03:34 +02:00
Robin Getz 63b6711cfa start adding some doc to the ./projects directory
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
2021-11-10 14:01:06 +02:00
LIacob106 58c1d2e3b2 projects: fixed xcvr clocks that generated critical warning 2021-11-09 12:40:14 +02:00
Laszlo Nagy 5ad40b29e5 adrv9001/zed: Use global clock buffers for better fit the design
Occasionally with zed, the implementation failed at the placement stage where
the tool could not fit the logic cells inside a single clock region,
constraint required by the usage of regional clock buffers.

This commit allows the usage of the global clock buffers which help the tool
in such cases and allow a larger application logic to be implemented in fabric.
2021-11-08 13:53:51 +02:00
Dan Hotoleanu 457c5f7d86 fmcjesdadc1: Fix ad9250 core parameters settings
Fix CONVERTER_RESOLUTION parameter setting for ad9250. Also deleted the
setting of BITS_PER_SAMPLE and DMA_BITS_PER_SAMPLE for ad9250 since they
are set by default to the desired values.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-04 12:18:06 +02:00
Stanca Pop bcf5abb2fe xmicrowave: Initial commit 2021-11-02 15:44:47 +02:00
hotoleanudan 1bc8a41aea
vc709_carrier: Add vc709 carrier (#788)
Added vc709 carrier to the projects/common folder location.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-11-02 12:05:42 +02:00
Laszlo Nagy c5d216bba9 adrv9001/zcu102: Enable independent TX mode in CMOS
For CMOS case, lane rates are so low that reference clock of the source
synchronous interface can be routed on non-clock routes. The delays on
the clock line are adjusted by the digital interface tuning controlled
through software.

Lock down clock buffers on Rx and Tx interfaces, this avoids suboptimal
placement which causes large skew between clocks at the serdes pins.
2021-10-27 14:40:08 +03:00
Laszlo Nagy 03682f6193 projects/adrv9001/zcu102/lvds_constr.xdc: Fix timing constraints
1. Reduce max allowed skew between source synchronous clocks that can
occur due PCB differences. 250ps represents a difference more than an
inch.

2. In order to reduce skew between source synchronous clock and the
divided clock instruct the tool to use a common clock root for them.
2021-10-27 14:40:08 +03:00
LIacob106 d4126739b4 projects: remove hardcoded div_clk from xcvr 2021-10-27 12:11:22 +03:00
sergiu arpadi cb861f5299 ad463x: Fix readme 2021-10-26 15:42:57 +03:00
Istvan Csomortani 15a6480601 ad4630_fmc: Initial commit 2021-10-18 16:13:31 +03:00
Mihaita Nagy ff090b60ef daq2/zcu102: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Mihaita Nagy 3640c2b584 daq2/kcu105: Fix the ad9144 data offload to use internal BRAM 2021-10-15 15:03:22 +03:00
Mihaita Nagy 6ad54c1056 daq2/kc705: Fix the ad9144 data offload to use internal bram 2021-10-15 15:03:22 +03:00
Mihaita Nagy 907cd613aa daq2/zc706: Increase BRAM utilization to 52% 2021-10-15 15:03:22 +03:00
LIacob106 e34346360d scripts: Add logic for vivado version check 2021-10-12 14:34:11 +03:00
Laszlo Nagy 5db7574dce scripts/adi_board.tcl: For older families stick with axi_interconnect
SmartConnect has higher resource utilization and worse timing closure
that makes several zed based projects to fail timing.
2021-10-07 14:18:49 +03:00
Filip Gherman 9295218a64 projects/ad9081_fmca_ebz: Updated makefiles 2021-10-05 16:56:57 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Laszlo Nagy 3a1babe366 ad9081_fmca_ebz/vck190: Reset GT with HMC7044 lock
Reset transceiver with a pulse
2021-10-05 14:09:51 +03:00
Laszlo Nagy 2562aead32 ad9081_fmca_ebz/common: Drive Rx DMA system side with DMA clock 2021-10-05 14:09:51 +03:00
Laszlo Nagy 8d547f31e1 ad9081_fmca_ebz/vck190: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 6c58a8d1ab ad9081_fmca_ebz/common: Add Versal transceiver support 2021-10-05 14:09:51 +03:00
Laszlo Nagy 56a25afa68 common/vck190: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 6a681b9e8d common/vmk180_es1: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 833e5f0aff common/vmk180: Initial version 2021-10-05 14:09:51 +03:00
Laszlo Nagy 2fec1356d6 scripts/adi_project_xilinx.tcl: VCK190 support 2021-10-05 14:09:51 +03:00
Laszlo Nagy 222c5782b6 scripts/adi_project_xilinx.tcl: Install ES1 board from XHUB, make project compile in batch mode 2021-10-05 14:09:51 +03:00
Laszlo Nagy 011c8c1f36 scripts/adi_project_xilinx.tcl: Add VMK180 & VMK180_ES1 support 2021-10-05 14:09:51 +03:00
Laszlo Nagy c22f622599 scripts/adi_board.tcl: Versal support for memory interconnect and irq interconnect 2021-10-05 14:09:51 +03:00
Laszlo Nagy 08c2ce75fe scripts/adi_board.tcl: Switch cpu_interconnect to SmartConnect 2021-10-05 14:09:51 +03:00
Laszlo Nagy aaaba50f83 scripts/project-xilinx.mk: Update target to xsa and cleanup list 2021-10-05 14:09:51 +03:00
LIacob106 0a986f76b8 scripts: QUARTUS_VERSION and PRO_ISUSED can be set in system_project.tcl 2021-10-02 12:34:10 +03:00
Adrian Costina 0a3724e04c s10soc: Update base desgin from ES to production, H-Tile version 2021-09-30 17:40:13 +03:00
Istvan Csomortani 5a3c3c878b ad9213_dual_ebz: Initial commit
Used ADF4377 SPI configuration CPOL/CPHA 1 for increasing the reliability of the level translators
ad9213_dual_ebz/s10soc: Redesign the address layout

avl_peripheral_mm_bridge 0x0000000 0x0001FFFF
  * sys_gpio_in  0x00000000
  * sys_gpio_out 0x00000020
  * sys_spi      0x00000040
  * sys_gpio_bd  0x000000D0
  * sys_id       0x000000E0

avl_mm_bridge_0 0x00040000 0x0007FFFF
  * ad9213_rx_0.phy_reconfig_0     0x00000000
  * ad9213_rx_0.phy_reconfig_1     0x00002000
  * ad9213_rx_0.phy_reconfig_2     0x00004000
  * ad9213_rx_0.phy_reconfig_3     0x00006000
  * ad9213_rx_0.phy_reconfig_4     0x00008000
  * ad9213_rx_0.phy_reconfig_5     0x0000A000
  * ad9213_rx_0.phy_reconfig_6     0x0000C000
  * ad9213_rx_0.phy_reconfig_7     0x0000E000
  * ad9213_rx_0.phy_reconfig_8     0x00010000
  * ad9213_rx_0.phy_reconfig_9     0x00012000
  * ad9213_rx_0.phy_reconfig_10    0x00014000
  * ad9213_rx_0.phy_reconfig_11    0x00016000
  * ad9213_rx_0.phy_reconfig_12    0x00018000
  * ad9213_rx_0.phy_reconfig_13    0x0001A000
  * ad9213_rx_0.phy_reconfig_14    0x0001C000
  * ad9213_rx_0.phy_reconfig_15    0x0001E000
  * ad9213_rx_0.link_pll_reconfig  0x00020000

avl_mm_bridge_1 0x00080000 0x000BFFFF
  * ad9213_rx_1.phy_reconfig_0     0x00000000
  * ad9213_rx_1.phy_reconfig_1     0x00002000
  * ad9213_rx_1.phy_reconfig_2     0x00004000
  * ad9213_rx_1.phy_reconfig_3     0x00006000
  * ad9213_rx_1.phy_reconfig_4     0x00008000
  * ad9213_rx_1.phy_reconfig_5     0x0000A000
  * ad9213_rx_1.phy_reconfig_6     0x0000C000
  * ad9213_rx_1.phy_reconfig_7     0x0000E000
  * ad9213_rx_1.phy_reconfig_8     0x00010000
  * ad9213_rx_1.phy_reconfig_9     0x00012000
  * ad9213_rx_1.phy_reconfig_10    0x00014000
  * ad9213_rx_1.phy_reconfig_11    0x00016000
  * ad9213_rx_1.phy_reconfig_12    0x00018000
  * ad9213_rx_1.phy_reconfig_13    0x0001A000
  * ad9213_rx_1.phy_reconfig_14    0x0001C000
  * ad9213_rx_1.phy_reconfig_15    0x0001E000
  * ad9213_rx_1.link_pll_reconfig  0x00020000

Connected directly to the h2s_lw_axi_master
  * ad9213_rx_0.link_reconfig      0x000C0000
  * ad9213_rx_0.link_management    0x000C4000
  * ad9213_rx_1.link_reconfig      0x000C8000
  * ad9213_rx_1.link_management    0x000CC000
  * axi_ad9213_0.s_axi             0x000D0000
  * axi_ad9213_1.s_axi             0x000D1000
  * axi_ad9213_dma_0.s_axi         0x000D2000
  * axi_ad9213_dma_1.s_axi         0x000D3800
2021-09-30 17:40:13 +03:00