In order to keep resource utilization low and for better timing closure
allow disabling of the character replacement logic.
If the parameter is set the frame alignment monitoring is limited to links
where scrambling is on.
Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode,
and frame alignment character replace/insert with or without scrambling.
Add support for xcelium simulator to jesd204/tb
Increased cores minor version.
There are boards (e.g. AD4630-24) which take the SCLK and echo back to
the FPGA through a level shifter - doing this removes the effect of
round-trip timing delays from the level shifter. This is commonly done
whenever isolators are used since they are very slow.
By setting the ECHO_SCLK parameter to 1, the IP will use the incoming
echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still
synchronous to the SPI clock, and it's generated after the last valid
SDI latch.
The designer's responsibility is to time the SDI shift registers in order to
respect the design requirements.
The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.
In phase aligned mode the fPLL uses an external feedback path to better
align the phase of the PLL output to the phase of the external reference
clock.
This mode is required for deterministic latency to be able to sample SYSREF
which is source synchronous to the external reference clock signal.
So far phase aligned mode had been disabled since manual PLL calibration
would fail in this mode under certain (unknown) circumstances and dynamic
reconfiguration of the PLL would not work.
The latest Intel Arria 10 transceiver datasheet contains instructions for
the proper calibration sequence to make it work when the PLL is configured
for phase aligned mode. Software has been updated accordingly, so enable
phase aligned mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Refactor the AXI4 stream FIFO implementation.
- Define a single address generator which supports both single and double
clock mode. (synchronous and asynchronous)
- Fix FIFO status bits (empty/full). NOTE: In asynchronous mode the
flags can have a several clock cycle delay in function of the upstream/downstream
clock ratio.
- In synchronous none FIFO mode (ADDRESS_WIDTH==0), the module acts as
an AXI4 stream pipeline.
Allow channels received from dma to re-map to other channels, e.g. allowing
broadcasting the same channel to all channels.
The feature is selectable with synthesis parameter and disabled by default.
Build a large mux from smaller ones defined by the REQ_MUX_SZ parameter
Use EN_REG to add a register at the output of the small muxes to help
timing closure.
This commit adds two fields:
1. source channel selection - Sets the channel number the for the source data.
2. DMA enable mask - When this bit is set do not drive the enable line
towards the DMA interface.
This feature will allow the user to hold(indefinitely) the last sample, from an
ongoing DMA transfer, simple or cyclic(stooped by user or trigger).
This commit also adds as functionality option:
-synchronized stop between the two channels(DMAs)
-stop by trigger
This reverts commit 0402ce85e4
and reverts commit 164aa97ec3.
The trigger pulse generation must be handled outside of the
SPI Engine framework.
It is recommanded to be done in system level using a PWM
generator or an external signal.
Laszlo Nagy
Matt Blanton
Istvan Csomortani
sergiu arpadi
Lars-Peter Clausen
AndreiGrozav
Adrian Costina