Commit Graph

28 Commits (e932e6f4f815d90c5f5a4c6236998789a01d9d93)

Author SHA1 Message Date
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters.
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Istvan Csomortani b54effc9c9 daq2/a10gx: Set optimization mode to aggressive performance 2020-08-17 10:43:03 +03:00
Istvan Csomortani 1c907b9248 daq2/a10gx: Use the default optimization mode 2020-08-11 10:14:18 +03:00
Istvan Csomortani 6e6f1347d7 project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani ec67a381e4 adi_project: Rename the process adi_project_altera to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani deb366d169 daq2|3: Set up OPTIMIZATION_MODE to improve timing
There are random timing violations on the A10GX board using the
DAQ3 and DAQ2 projects.

Setting the synthesis/implementation strategy to "HIGH PERFORMANCE
EFFORT" increases the success rate of the timing closure significantly.
2018-06-06 08:33:20 +01:00
Lars-Peter Clausen 17d3e3c64b daq2: daq2_qsys.tcl: Convert to ADI JESD204
Convert the DAQ2 project for Intel/Altera platforms to the ADI JESD204
framework.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:21:42 +02:00
Rejeesh Kutty 3f92381bd0 daq2/a10gx- project/constraint updates 2017-06-06 16:09:15 -04:00
AndreiGrozav b78e9d8c27 daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V 2017-03-01 11:32:17 +02:00
Rejeesh Kutty 5df30ac6b0 daq2/a10gx- xcvr sharing 2016-09-12 14:57:50 -04:00
Istvan Csomortani f784557895 lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera 2016-08-08 15:06:34 +03:00
Rejeesh Kutty ae1dd1d58e daq2/a10gx- qsys updates 2016-06-07 12:28:04 -04:00
Adrian Costina ea57b3c03c daq2: A10GX, add project specific IP search paths 2015-11-25 10:58:36 +02:00
Adrian Costina a81625e1fa daq2: Updated a10gx project 2015-11-24 13:28:53 +02:00
Rejeesh Kutty 827fc1e29a remove auto-pack disable 2015-08-20 13:54:16 -04:00
Rejeesh Kutty 0e587dd955 daq2/a10gx-- ad-rst unpack 2015-08-19 13:26:38 -04:00
Rejeesh Kutty b3102b5095 daq2/a10gx-- xcvr+base changes 2015-07-21 11:01:45 -04:00
Rejeesh Kutty 4b8d764852 daq2- base system modifications 2015-07-20 09:31:44 -04:00
Rejeesh Kutty a2e7fb9491 daq2/a10gx: qsys signal tap version 2015-07-13 10:07:18 -04:00
Rejeesh Kutty 8c0d74aa90 transceiver split up outside qsys 2015-07-10 11:44:42 -04:00
Rejeesh Kutty f1dd2435b4 signal tap removed 2015-07-08 15:47:31 -04:00
Rejeesh Kutty 6bc24e25eb stap- need to be qsys 2015-06-29 13:26:32 -04:00
Rejeesh Kutty 67df6b3ea8 a10gx- disable lab cell on dsp input register 2015-06-19 14:32:54 -04:00
Rejeesh Kutty 4a701d3895 a10gx- no-ddr 2015-06-01 11:00:02 -04:00
Rejeesh Kutty ad3198f623 a10gx: top level fixes 2015-05-21 14:06:15 -04:00
Rejeesh Kutty dc0eea5f0f a10gx: updates-- 2015-05-11 11:56:26 -04:00
Rejeesh Kutty 75e055dab9 daq2/a10gx- initial commit 2015-05-11 11:56:23 -04:00