c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
4f4825a3df
projects:daq2:common: fix adi_tpl_jesd204_rx_create error. ( #952 )
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(\ character has to be removed or a blank line inserted before ad_ip_parameter)
Fix for : 0b8585a6f
2022-06-06 08:53:07 +03:00
0b8585a6f1
PN mismatch DAQ2, DAQ3 and FMCJESDADC1 fix ( #950 )
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The AD9680 is a dual 14-bit ADC.
Software sets the output format to offset binary before performing the PN tests.
2022-06-02 14:09:36 +03:00
0e55583a63
daq2: Do not set AXI address width for DO
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Address size and memory ranges are automatically computed by the
external storage interfacing IP (util_hbm) based on the storage size and
base address so this parameter is redundant.
2022-04-28 14:31:32 +03:00
530aca9754
daq2: Parameterize JESD204 configuration values
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Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-20 12:54:03 +02:00
b354d517f5
daq2: Connected loose ad9144 dunf flag that fixes the critical warning
2021-08-20 10:38:52 +03:00
dc910420bd
daq2: Integrate data_offload
2021-08-06 11:55:24 +03:00
137c31db1d
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-18 15:45:19 +03:00
019390f9bf
block_design: Updates with new reset net variables
2019-06-11 18:13:06 +03:00
7960b00684
block_design: Update with new clock net variables
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Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
9b048f1a0e
daq2: update adcfifo/dacfifo
2019-01-23 14:45:45 +02:00
d8e11cfce5
daq2/3: update DAC TPL base addresses
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The TPL for DACs can be relocated to addresses which match the software
expectations.
2018-12-04 14:02:22 +02:00
b9958cac00
daq2: Use new pack/unpack infrastructure
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Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
97b1d3a21e
common/daq2: Fix typo
2018-08-23 15:13:58 +03:00
87b099d498
daq2/common: Add default util_adxcvr parameters
2018-08-21 17:12:31 +03:00
b9b619d918
axi_ad9144: Hide unused ports in DUAL mode
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In DUAL mode half of the data ports are unused and the unused inputs need
to be connected to dummy signals.
Completely hide the unused ports in DUAL mode to remove that requirement.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 17:21:20 +02:00
5075be8bff
daq2: Connect the DAC data underflow
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Connect the DAC data underflow pin (fifo_rd_underflow) of the DMA
to the dunf pin of the device core. This way the software can detect
underflows in the DAC data path.
2018-04-13 18:46:29 +03:00
7f377454a8
daq2/fmcadc4/daq3: Disable the transfer start sync on the ADC DMA
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Explicitly disable the "Transfer Start Synchronisation Support"
since the sync lines are not connected in this project.
If the sync input line (s_axi_user[0] or fifo_wr_sync) are not connected,
Vivado 2017.4.1 no longer connects them to the defaultValue defined
in the axi_dmac ip (1). Instead he uses the defaulValue field defined
in the interface definition which in case of both interfaces is 0;
2018-04-11 15:09:54 +03:00
207f00a752
projects/ remove upack dma_xfer_in
2017-07-31 09:12:05 -04:00
0360e8587e
Connect JESD204 interrupts
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Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
2e8be3d7a6
daq2: Provide DAC lane map
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Provide the correct lane mapping for the DAQ2 DAC lanes which do not follow
a 1-to-1 mapping between physical and logical lanes due to PCB layout
constraints.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
0ec92d3153
daq2: Convert to ADI JESD204
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Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is
very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
454e6c0382
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 13:04:53 -04:00
191669ad28
daq2_common: Fix the dac_rst for DAC FIFO
2017-03-07 16:13:46 +02:00
4a6fe54fcf
daq2_common: Update common scripts
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Add new port connection for util_dacfifo
2017-03-03 18:49:10 +02:00
6b1a8852a9
dacfifo- bypass port name change
2017-02-27 16:06:39 -05:00
daa3df4b96
projects/- xcvr updates
2016-11-22 16:23:05 -05:00
b1a9bd96f1
daq2: xcvr pll changes
2016-11-22 12:53:29 -05:00
3b55822db3
daq2- xcvr connect
2016-10-06 14:09:27 -04:00
ed9e92621c
daq2- spi+xcvr address conflict
2016-08-04 10:50:31 -04:00
9952a94efb
hdl-vivado-2016.2- ip version updates
2016-07-28 13:44:57 -04:00
6df5ba1a7a
daq2- adxcvr version
2016-07-21 16:09:33 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
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hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
1fab6ce477
daq2/common: Add util_dacfifo/dac_xfer_out control
2016-03-29 16:55:33 +03:00
b7be089b82
daq2: Updated common design to 2015.4
2016-03-16 10:02:42 +02:00
7184827d68
daq2: Drop explicit axi_dmac clock synchronicity configuration
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The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:54 +02:00
58fa29b673
daq2- jesd core upgrade
2015-08-27 11:18:00 -04:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
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Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
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The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
c72cf99562
daq2- gt changes
2015-08-17 14:11:58 -04:00
4c80013faf
projects/daq2: gt lane split
2015-06-12 15:56:03 -04:00
e6525136a9
daq2/common: axi_ad9144_fifo needs a proper reset sequence
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Connect the axi_ad9144_fifo/dma_rst signal to sys_cpu_reset
2015-06-12 14:03:46 +03:00
e3e4af5c51
daq2/zc706: open ports
2015-06-10 14:25:58 -04:00
f9ffaf457d
projects/daq2- drp moved to up clock
2015-06-01 13:39:26 -04:00
15618c9edf
daq2 : Integrate the DACFIFO into the supported projects.
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+ All pack/unpack logic is made by the cpack and upack modules.
+ The DAC FIFO is integrated between the TX DMA and cpack.
+ All the top files are updated, all the projects compiled successfully.
2015-05-11 12:20:50 +03:00
e332fa01c8
ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection
2015-04-30 12:11:46 +03:00
ff3dcbc2cb
daq2: move intrs into ipi
2015-03-12 16:16:55 -04:00
548ae9d39e
daq2: move gpio/spi to base design
2015-03-09 16:08:25 -04:00
d5eaadd872
daq2: remove ila for kcu105 ddr-300M timing
2015-03-06 12:38:08 -05:00
605d23d3a4
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
Iulia Moldovan
PopPaul2021
Laszlo Nagy
Dan Hotoleanu
Mihaita Nagy
Istvan Csomortani
Lars-Peter Clausen
AndreiGrozav
Rejeesh Kutty
Shrutika Redkar
Adrian Costina