293ec6a319
fmcomms2: c5soc project updated to 14.1
2015-05-08 17:44:16 +03:00
c7989925c5
fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock
...
Otherwise we get timing errors for the reset signal that is generated in the
50MHz clock domain, but used in the VGA PLL clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
9a08189b93
c5soc: initial a5soc copy
2014-07-01 13:09:38 -04:00
Adrian Costina
Lars-Peter Clausen
Rejeesh Kutty