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27 Commits (eba22892b8de0f603e1841c2f3528c2f7988c7db)

Author SHA1 Message Date
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Istvan Csomortani ccf1c56b33 util_upack: Patch up the description of Altera IP 2016-08-08 16:39:56 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty c293c04634 hdl make updates 2016-06-01 13:53:09 -04:00
Rejeesh Kutty 7fdaee186c upack/cpack- qsys ip 2016-05-18 13:24:13 -04:00
Rejeesh Kutty e15893444c upack- fix interface names 2016-05-18 13:24:13 -04:00
Adrian Costina 0d67af370f util_upack: Fixed problem when dac valid isn't continuous from the DAC 
In cases when the dac_valid_ from the DAC is not continuous, in some situations
there were two dac_valid pulses sent to the DMA.
 2016-02-04 13:03:46 +02:00
Adrian Costina e6de2ade78 util_upack: Updated altera interfaces 
- DMA side, simplified naming
- DAC side, added FIFO conduit per channel
 2015-11-24 11:17:02 +02:00
Adrian Costina e5d2f5be06 util_upack: Cosmetic changes 2015-11-24 10:55:10 +02:00
Rejeesh Kutty f3410a7db1 xpack- remove useless interfaces 2015-08-26 14:12:14 -04:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters 
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
 2015-08-19 14:11:47 +03:00
Rejeesh Kutty 3101045109 qsys- library group 2015-07-17 10:07:15 -04:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Rejeesh Kutty da8915296b pack: ip scripts 2015-06-05 09:20:08 -04:00
Adrian Costina 2b5abf74d7 util_upack: Show upack_valid only if the channel is activated 2015-06-02 11:36:06 +03:00
Rejeesh Kutty dc2eeebf2f upack: gen-name 2015-05-21 14:06:12 -04:00
Rejeesh Kutty da0409b5a6 library- qsys components 2015-05-20 11:51:50 -04:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all 
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
 2015-04-17 17:22:38 +03:00
Adrian Costina 374f82e7de makefiles: The clean command for library won't remove the xml files, except for component.xml. 
Updated also the dmac dependencies
 2015-04-16 11:53:27 +03:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Adrian Costina de2c3764d6 util_upack: Updated IP, added upack_valid and dma_xfer_in/dac_xfer_out ports. 2015-04-07 16:55:25 +03:00
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty 2f41aebaa9 makefile: added 2015-04-01 16:28:19 -04:00
Adrian Costina 7e15fd9e5b util_upack: Fixed ip 2015-03-19 16:22:12 +02:00
Rejeesh Kutty 518d842af9 upack: initial commit 2015-02-06 15:15:33 -05:00