3 Commits (ebfed4b24bc333d45d4e2e94b1fca602c6cbbf00)

Author	SHA1	Message	Date
Istvan Csomortani	ac2e5a9dac	constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.	2017-02-24 13:43:32 +02:00
Adrian Costina	358aa48c76	axi_adc_decimate: Fix assignment width	2017-02-15 11:38:43 +02:00
Adrian Costina	4a7232cbcb	axi_adc_decimate: Initial commit	2017-01-31 16:21:39 +02:00