4 Commits (ed20d00f77a964628b13985ec31eef8b0ed18982)

Author	SHA1	Message	Date
Rejeesh Kutty	fb4a583613	projects/system_bd- adc/dac fifo board designs	2017-02-27 16:06:39 -05:00
Rejeesh Kutty	edd5e9570f	file renamed; sed output; fingers crossed	2017-02-22 15:56:37 -05:00
Istvan Csomortani	7be017baa3	daq1: Add AXI PLDDR FIFO to the receive path ... The AD9684 has two 500 MSPS converter, the system can not handle this throughput without a FIFO.	2016-07-07 07:15:54 +03:00
Istvan Csomortani	ee752ec08a	daq1: Initial commit	2014-09-01 18:34:31 +03:00