Istvan Csomortani
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2330d1e27d
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daq1/common: The new GT module does not have integrated monitor/debug ports
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2015-06-09 11:50:27 +03:00 |
Rejeesh Kutty
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71b5004b25
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projects- drp moved to up-clock domain
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2015-06-01 14:57:59 -04:00 |
Adrian Costina
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3b58785368
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daq1: Updated jesd reset connection. Fixed dmac async configuration. Updated zc706 constraints
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2015-04-30 12:14:03 +03:00 |
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Istvan Csomortani
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75d2c7e93e
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daq1_zc706: Update project to the new framework
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2015-03-24 12:45:24 +02:00 |
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Istvan Csomortani
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68ac015825
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daq1_fmcl: Fix GT lane number definitions
Update which fix issues caused by GT lane number parameters change. (commit f8e7796592)
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2014-11-24 18:23:33 +02:00 |
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Istvan Csomortani
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0ecfc14e95
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daq1_fmc: Update interrupts.
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2014-11-24 18:23:32 +02:00 |
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Istvan Csomortani
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9b104f1657
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daq1_fmc: Get rid of the concat module inside the block design.
xl_concat just causing troubles, no need to use it, if not justified.
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2014-11-24 18:23:30 +02:00 |
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Istvan Csomortani
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17675863e0
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all_projects: Fix the interrupt connections to preserve IRQ layout
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2014-10-22 11:48:08 +03:00 |
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Rejeesh Kutty
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577441bd0c
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daq1: clean up dma interfaces
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2014-09-23 14:23:41 -04:00 |
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Istvan Csomortani
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dd7bac41c1
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daq1 : Update project to 2014.2
- Cores are upadted
- Concat module does not swap output anymore
- Clock signal name ps7_clk_* changed to clk_fpga_*
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2014-09-22 17:33:50 +03:00 |
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Istvan Csomortani
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a91f4bb6b9
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daq1: General updates
- Add additional GT setups
- Use channel PLL instead of quad PLL
- Add additional ILA probes for debug
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2014-09-13 00:23:11 +03:00 |
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Istvan Csomortani
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ee752ec08a
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daq1: Initial commit
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2014-09-01 18:34:31 +03:00 |