Commit Graph

10 Commits (ed6bdf66bdcf7d63ea8a0697b98d6c3fff84e17b)

Author SHA1 Message Date
Lars-Peter Clausen bd6c76f4ab fmcomms5: Set DMA AXI type to AXI3 on ZYNQ
The HP memory ports on ZYNQ are AXI3. The AXI-DMAC supports both native AXI3
and AXI4, by configuring it for AXI3 there is no need for a protocol
converter inside the interconnect, that connects the DMAC to the HP port.

In addition to that also set the data width for the DMAC on the HP port side
to 64 so there is no need for a memory width converter in the interconnect.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
Adrian Costina 51b5e4ddc5 fmcomms5: Moved the clock generation for dma transfer inside system_bd of the platform 2015-04-02 22:29:17 +03:00
Adrian Costina 92aa58826d fmcomms5: Updated project to be compatible with both ZC702 and ZC706 2015-03-31 17:42:44 +03:00
Adrian Costina 1828a94446 fmcomms5: Updated common and ZC706 project to the latest framework 2015-03-25 17:42:11 +02:00
Adrian Costina 0ade2a5f67 fmcomms5: Updated project to vivado 2014.2. Updated interrupt system. Fixed constraints 2014-11-07 13:45:15 +02:00
Istvan Csomortani 17675863e0 all_projects: Fix the interrupt connections to preserve IRQ layout 2014-10-22 11:48:08 +03:00
Adrian Costina 7000897031 fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
Rejeesh Kutty b434fe6dd5 fmcomms5: register map changes 2014-07-08 16:57:43 -04:00
Rejeesh Kutty bab90a19c2 fmcomms5/zc702: removed unused ila cores 2014-05-20 14:42:48 -04:00
Rejeesh Kutty 9a36075324 moved fmcomms5 2014-05-19 13:49:49 -04:00