103cbe73dc
intel/adi_jesd204: Add support for external core clock
...
In Subclass 1 mode, we need to use a separate clock (device clock) to
drive the link and transport layer of the interface. Implement the
required infrastructure for this scenario.
The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-10-02 15:32:17 +03:00
aeaefd2c1c
intel/jesd204_phy: Add support for external coreclkin
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In Subclass 1 mode an external device clock (core clock) is used,
instead of the PCS output clock, to drive the link and transport layer.
Define an additional parameter, which can be used to enable clock input
port for the PHY module, which can be used as rx|tx_coreclkin source.
2019-10-02 15:32:17 +03:00
e45f014138
intel/axi_adxcvr_up: Add device spec register
2019-10-02 08:39:01 +03:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
fe09acaa2f
up_axi_update: ADDRESS_WIDTH parameter is now a localparam
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ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2;
up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
2019-07-26 11:58:58 +03:00
3031ec3bdd
adi_jesd204: Move some leftover files to intel directory
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These file were left in the old library directory, move them to the new
library/intel directory.
2019-07-10 10:57:12 +01:00
76620bc890
avl_adxcvr: Rename variables with alt_* pre-fix
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- alt_sys_clk -> sys_clk
- alt_xcvr_rst -> xcvr_rst
- alt_ref_clk -> ref_clk
- alt_fpll_rst_cntrol -> fpll_rst_control
- alt_core_pll -> core_pll
- alt_core_clk -> core_clk
- alt_rst_cntrol -> rst_control
- alt_lane_pll -> lane_pll
- alt_ip -> jesd204_ip
- alt_xphy -> avl_xphy
- alt_phy_* -> phy_*
2019-06-29 06:53:51 +03:00
0f7a3b953a
scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface
2019-06-29 06:53:51 +03:00
04ce10a570
cosmetics: Change Altera to Intel in comments
2019-06-29 06:53:51 +03:00
2f0dbe6151
intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym
2019-06-29 06:53:51 +03:00
1e074726db
intel_serde: Rename alt_serdes to intel_serdes
2019-06-29 06:53:51 +03:00
b0fbe1bb57
util_clkdiv: Seperate the IP source into an intel and xilinx version
2019-06-29 06:53:51 +03:00
84bd50d437
alt_ifconv: Remove unused IP
2019-06-29 06:53:51 +03:00
d5e5fcf17a
alt_mul: Remove unused IP
2019-06-29 06:53:51 +03:00
5329458a62
library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
Istvan Csomortani
AndreiGrozav
Arpadi