041d8faaf7
common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2
2014-09-30 10:31:00 +03:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
a49eb5853b
ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
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For ZC706 Fixed one constraint which was not correct
2014-08-26 16:28:41 +03:00
f9a67371c0
Zynq Base System: Reset is synchronized to lowest system clock
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System reset (sys_100m_reset) is synchronized to lowest system
clock (FCLK0), via a Processor System Reset module
2014-03-26 17:58:14 +02:00
dc44703cf1
zynq/non-zynq: identical signal names and instances
2014-03-17 17:02:03 -04:00
f3ae57a53e
global clock and reset names
2014-03-11 09:57:59 -04:00
ddac1a8834
added common board files
2014-02-28 21:17:01 -05:00
Adrian Costina
Lars-Peter Clausen
Istvan Csomortani
Rejeesh Kutty