Commit Graph

9 Commits (ee01ea3736f85e5728138e8651daf06cfeb8684e)

Author SHA1 Message Date
Istvan Csomortani 899b8436ad arradio: Fix the last incorrect merge 2017-10-03 09:15:45 +01:00
Istvan Csomortani 89bd8b44d4 Merge branch 'dev' into hdl_2017_r1 2017-09-26 07:42:19 +01:00
Rejeesh Kutty 6d788ebb3a arradio- remove dma_xfer_in from upack 2017-07-28 16:19:24 -04:00
Lars-Peter Clausen d7e87a60a9 Remove executable flag from non-executable files
All of these files are source code and are not executable standalone.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 17:56:07 +02:00
Adrian Costina 53ca4f6ac9 arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits
This fixes the bandwidth issue when data is streamed from the DDR and the system works at 61.44 MSPS
2017-07-28 10:11:55 +01:00
Adrian Costina 31143cb893 arradio: Changed clock domain of the ADC and DAC path to half the interface clock 2017-07-27 13:40:41 +01:00
Lars-Peter Clausen 374c49ff48 axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains
Qsys allows to query to query the clock domain that is associated with a
clock input of a peripheral. This allows to automatically detect whether
the different clocks of the DMAC are asynchronous and CDC logic needs to be
inserted or not.

Auto-detection has the advantages that the configuration parameters don't
need to be set manually and the optional configuration will be choose
automatically. There is also less chance of error of leaving the settings
in a wrong configuration when e.g. the clock domains change.

In case the auto-detection should ever fail configuration options that
provide a manual overwrite are added as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 16:06:37 +02:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty 7dfa8c599f arradio/c5soc- updated to new framework/16.0 2017-03-20 12:15:18 -04:00