Fix the following warnings that are generated by Quartus:
Warning (10236): Verilog HDL Implicit Net warning at util_dacfifo.v(257): created implicit net for "dac_mem_ren_s"
Warning (10230): Verilog HDL assignment warning at util_dacfifo.v(166): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at util_dacfifo.v(266): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at util_dacfifo.v(268): truncated value with size 32 to match size of target (10)
No functional changes.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
In cases when a shallow FIFO is requested the synthesizer infers distributed RAM
instead of block RAMs. This can be an issue when the clocks of the FIFO are
asynchronous since a timing path is created though the LUTs which implement the
memory, resulting in timing failures. Ignoring timing through the path is not a
solution since would lead to metastability.
This does not happens with block RAMs.
The solution is to use the ad_mem (block RAM) in case of async clocks and letting
the synthesizer do it's job in case of sync clocks for optimal resource utilization.
The grey coder/decoder function was limited to 10 bits, and this
resulted an unwanted limitation of the FIFO size. Using this
module, the coder/decoder data width can be adjusted to the current
address width.
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
+ Clean out the code, delete unnecessary flops
+ Add support for channel count (C_CH_CNT)
+ FIFO write (data from DMAC/upack) : valid just when xfer_req is asserted, address is free running, new xfer_req resets the address
+ FIFO read (data to DAC) : free running, reads to max address
Lars-Peter Clausen
Laszlo Nagy
Istvan Csomortani
Rejeesh Kutty