Commit Graph

340 Commits (ee8742141951eed449219fab5b286569dc86cbac)

Author SHA1 Message Date
Adrian Costina 7e15fd9e5b util_upack: Fixed ip 2015-03-19 16:22:12 +02:00
Adrian Costina bc04e5a4ce axi_i2s_adi: Fixed pins directions 2015-03-12 17:22:52 +02:00
Rejeesh Kutty 8dfcbdfd48 gt_channel/gt_common: simulation parameter warning fix 2015-03-06 12:36:07 -05:00
Rejeesh Kutty 57e1f0e334 gt_channel/gt_common: simulation parameter warning fix 2015-03-06 12:36:03 -05:00
Rejeesh Kutty 2d01955042 up_gt: change version dfe/lpm support 2015-03-05 09:47:16 -05:00
Istvan Csomortani 6995f63134 Add version check to adi_ip.tcl too. 2015-03-05 11:55:09 +02:00
Istvan Csomortani 1613f7fb41 cftl_cip: Add util_pmod_fmeter IP to library
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
Lars-Peter Clausen 65bda6505e axi_dmac: Correctly handle shutdown for the request splitter
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
Lars-Peter Clausen 731e1c0996 axi_dmac: Use internal enable signal for the request generator
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
Lars-Peter Clausen 582ea06918 axi_dmac: request_generator: Stop generating requests when disabled
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.

So just stop generating burst requests once the DMAC is being disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:23 +01:00
Lars-Peter Clausen aa594e15f3 axi_dmac: fifo_inf: Handle overflow and underflow correctly
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-19 17:22:21 +01:00
Rejeesh Kutty 6edcaa478a adi_ip: updates for 2014.4 2015-02-19 11:11:39 -05:00
Rejeesh Kutty 9cdec38532 gt- report device type 2015-02-17 11:43:57 -05:00
Rejeesh Kutty 2442b6e929 gt- report device type 2015-02-17 11:43:50 -05:00
Rejeesh Kutty fccadcec31 jesd_gt: lpm/dfe programmable 2015-02-13 11:33:25 -05:00
Rejeesh Kutty de043ce130 gt_channel: lpm/dfe programmable 2015-02-13 11:33:04 -05:00
Rejeesh Kutty 870ebdb562 up_gt: support lpm mode 2015-02-12 16:21:11 -05:00
Rejeesh Kutty 1e7c9a3924 gt_es: support lpm mode - 2/2 2015-02-12 16:20:43 -05:00
Rejeesh Kutty 0a8e6f62ef gt_es: support lpm mode - 1/2 2015-02-12 15:15:18 -05:00
Rejeesh Kutty 9e2e2ef44e xfer-logic: stretch toggles to allow capture 2015-02-06 22:15:16 -05:00
Rejeesh Kutty e9231c8f36 xfer-logic: stretch toggles to allow capture 2015-02-06 22:15:14 -05:00
Rejeesh Kutty 518d842af9 upack: initial commit 2015-02-06 15:15:33 -05:00
Istvan Csomortani d02c21b426 util_pmod_adc: General update
Redesign the state machine, rename constant and variable names, add notes and description.
2015-02-04 14:49:16 +02:00
Istvan Csomortani 96899313d8 axi_dmac: Fix constraint
Change the constraint file extension to .xdc, no more need for the .tcl workaround.
2015-01-23 18:51:25 +02:00
Istvan Csomortani b10ba49425 axi_dmac: Fix constraint related issue
Tcl command "if" is not supported by Vivado XDC, therefore the tool throw some critical warnings, and does not
apply the constraints, which can cause timing violations at case of some carriers.
The following solution is much more compact and is supported by the XDC, and more importantly prevents
unwanted critical errors and timing violations.
2015-01-23 18:44:17 +02:00
Istvan Csomortani d5bd485624 axi_dmac: Fix eot issue under 2014.4
Vivado 2014.4 is too greedy, when it needs to optimize. See more about the issue here: https://ez.analog.com/thread/48214
The response_dest_resp is unused, so not save to concatenate with a valid signal like the eot.
2015-01-23 18:39:33 +02:00
Istvan Csomortani 659e0cca4e cftl_cip: Initial check in.
Project cftl_cip supports the following Circuits from the Lab pmods:
 + EVAL-CN0350-PMDZ
 + EVAL-CN0335-PMDZ
 + EVAL-CN0336-PMDZ
 + EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
Rejeesh Kutty 5a1819ed6e fifo2s: qualify last with valid 2015-01-15 15:42:10 -05:00
Rejeesh Kutty debbe31713 Merge remote-tracking branch 'origin/master' into dev 2015-01-09 11:12:56 -05:00
Rejeesh Kutty 63633a0fa5 ad9739a: constraints 2015-01-08 10:25:45 -05:00
Rejeesh Kutty ed73a9d1cf ad9739a: updated to ad9739a 2015-01-08 10:25:15 -05:00
Istvan Csomortani 14df46c193 library: Initial commit of axi_hdmi_rx ip core
Status unknown, NOT tested.
2015-01-08 16:58:56 +02:00
Istvan Csomortani 9f485f2f4e common: Add register map module for HDMI receiver. 2015-01-08 12:24:47 +02:00
Istvan Csomortani 161e6cc70d common: Add color space sampling and color space conversion modules
This two module are used by the HDMI receiver.
2015-01-08 12:24:46 +02:00
Rejeesh Kutty ad4b4f64d0 ad9739a: ad9122 copy 2015-01-07 15:36:02 -05:00
Rejeesh Kutty 3a4d765a2b up_clkgen: reading typo 2015-01-07 14:02:39 -05:00
Rejeesh Kutty b65bcab8d6 up_clkgen: reading typo 2015-01-07 13:58:43 -05:00
Rejeesh Kutty 5f93c859b5 util_rfifo: renamed ports to make vivado happy 2015-01-06 16:16:42 -05:00
Rejeesh Kutty 8056574bae util_wfifo: renamed ports to make vivado happy 2015-01-06 16:16:25 -05:00
Rejeesh Kutty 0291bb3bf7 util_rfifo: port name fixes & doc. 2015-01-06 16:15:51 -05:00
Rejeesh Kutty 36b041ccc0 util_wfifo: port name fixes & doc. 2015-01-06 16:15:42 -05:00
Rejeesh Kutty ee0912eb6a ad9361: make 2t2r external for mw 2015-01-05 10:54:23 -05:00
Rejeesh Kutty c3529f112f up_gt: move status to up clock 2014-12-19 13:00:27 +02:00
Rejeesh Kutty f4774d6f98 fifo2s: false path typo on source signals 2014-12-19 13:00:13 +02:00
Rejeesh Kutty 1d6ea64d04 up_gt: move status to up clock 2014-12-16 08:48:13 -05:00
Rejeesh Kutty 16f64a75d6 fifo2s: false path typo on source signals 2014-12-15 13:00:13 -05:00
Rejeesh Kutty 04c10abc2f gth/gtx: share same cpll/qpll cpu settings 2014-12-11 11:18:48 -05:00
Istvan Csomortani c4152627f0 plddr3: Sync adc_wcnt_int to adc_wr and fix adc_dwr pulse width
The adc_wcnt_int must be synchronized to adc_wr. The adc_dwr signal pulse width was to long,
it needs to be just one adc_clk cycle.
2014-12-09 13:59:19 +02:00
Istvan Csomortani 19732d89fb plddr3: Fix the adc_dwr pulse width
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
2014-12-09 13:51:00 +02:00
Adrian Costina 6aad2fbbb2 axi_hdmi_tx: Fixed typo in altera related core 2014-12-09 10:19:03 +02:00