Commit Graph

2667 Commits (eedb2ce0f497561b2c04dc83a0757161702e413f)

Author SHA1 Message Date
Laszlo Nagy 7f16f823ff Revert "axi_dmac: add tlast to the axis interface for Intel"
This reverts commit e2c75c015f.
2019-05-16 13:27:19 +03:00
Istvan Csomortani 7b26190716 fmcomms11: By default we support complex mode 2019-05-16 13:26:58 +03:00
Istvan Csomortani cf03e216fe fmcomms11: Update the project with the new TPL 2019-05-16 13:26:58 +03:00
Istvan Csomortani eba1975144 fmcomms11: Initial commit 2019-05-16 13:26:58 +03:00
Sergiu Arpadi 7ae2bc6285 adi_project: used report_timing_summary to evaluate timing 2019-05-09 12:27:35 +03:00
Sergiu Arpadi 17c20eeb7a adi_project: Fix timing check
Fixed timing paths evaluation where there is no logic in PL.
2019-05-09 12:27:35 +03:00
Istvan Csomortani 31e7c8e778 zc706/plddr3_adc|dacfifo_bd: PL DDR3 size is 1Gbyte 2019-05-06 17:17:00 +03:00
Laszlo Nagy 2c2be2f38a scripts: patch incremental compile
Clear the reference checkpoint if the incremental compilation is not
selected through the make option. Other case the scripts will silently
use the reference.dcp checkpoint if that exists.
2019-04-23 18:07:55 +03:00
Laszlo Nagy 525c068993 scripts: Support for incremental compilation
The scripts are looking for a previous run result, a routed design
checkpoint to use it as a reference during the incremental build flow.
Before clearing the project files, the scrips will save the reference dcp
file in the project folder.
If the reference dcp does not exists the build continues normally.

Proposed workflow:
  1. Build your project normally with 'make' or place manually a
  reference.dcp file in the Vivado project folder.
  2. Do some minor modifications
  3. Run the make with the following option:
    make MODE=incr
  4. Repeat steps 2-3
2019-04-22 10:27:16 +03:00
Laszlo Nagy 5b13e205b9 axi_mc_controller:axi_mc_current_monitor: define generated clocks in IP constraints file for better OOC integration 2019-04-22 10:27:16 +03:00
Laszlo Nagy 5dd9cdcdea scripts: Add common IP cache location for OOC mode
Using a common IP cache location for all the project will speed up
compile time of common blocks used in base designs. Example a MicroBlaze
core for VCU118 once compiled it will be reused on other projects.

Using a common IP cache will speed up re-compiles of every project in OOC
mode since the cache won't be cleared as with normal compile flow.
2019-04-22 10:27:16 +03:00
Laszlo Nagy 5e92dc45b2 scripts: add support for OOC synthesis flow
Usage:
from command line set any value to the ADI_USE_OOC_SYNTHESIS variable
e.g. export ADI_USE_OOC_SYNTHESIS=y
2019-04-22 10:27:16 +03:00
Adrian Costina f5ed5def27 daq3: vcu118 initial commit 2019-04-17 14:24:35 +03:00
Adrian Costina dc5f90098e vcu118: Initial commit for common files 2019-04-17 14:24:35 +03:00
Adrian Costina 844a848d2d pluto: Removed interconnects to HP ports to reduce utilization 2019-04-15 17:49:11 +03:00
Adrian Costina d80692da03 m2k: Remove memory interconnects and connect directly to the HP ports
Vivado generates errors with the smartconnect change, altough the interconnect should be synthesized out
2019-04-15 17:49:11 +03:00
Adrian Costina 660f66af98 kcu105: Moved to smartconnect 2019-04-15 17:49:11 +03:00
Adrian Costina 77cc0ce8ba scripts: adi_board.tcl, move from memory interconnect to smartconnect 2019-04-15 17:49:11 +03:00
AndreiGrozav 7ce39c4000 adrv9361z7035_ccbob_cmos: Use ad_rst constraints file
The file was excluded by mistake.
2019-04-12 10:48:50 +03:00
Laszlo Nagy 4b13274c55 ad9361/all/system_constr.xdc: remove manual clock definition
Having a clock assigned manually to the clk output pin of the axi_ad9361
let the Vivado timing engine to not ignore the clock insertion delay when
analyzing paths between clk_0 and the manually created clock that has
the same source (clk_0), resulting in timing failure.
2019-04-12 10:48:50 +03:00
AndreiGrozav bd79a0040e common/vc707: Tools version update (2018.3)
Use 200MHz clock for Ethernet subsystem ref_clk
2019-04-12 10:48:50 +03:00
AndreiGrozav e1f0b301d3 Tools version upgrade
Vivado 2018.2 -> Vivado 2018.3
Quartus 18.0  -> Quartus 18.1
2019-04-12 10:48:50 +03:00
AndreiGrozav d894c30c2d Remove deprecated/unused parameters
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
2019-03-30 11:26:11 +02:00
Laszlo Nagy 8885caab13 scripts/adi_board.tcl: fix HP address mappings for ZynqMP
In the current form, when connecting a master to the HP ports all
available slave address spaces are mapped to the master (DDR_*, PCIE*, OCM,
QSPI)

Let the PL masters have access only to the DDR_LOW and DDR_HIGH address
spaces to avoid unnecessary resource usage and increase timing margin.
2019-02-27 15:04:41 +02:00
Adrian Costina 6e9bc398c3 fmcomms5: Connect overflow pin between adc_pack and adc_fifo 2019-02-14 14:36:45 +00:00
AndreiGrozav ce04f46b80 motcon2_zed: Fix timing problems
-change implementation strategy
-axi_dmac add extra registers AXI_SLICE_SRC

This was done to increase the overall timing margin.
2019-02-12 10:43:46 +02:00
AndreiGrozav 2d825d8b7c daq3_zc706: Change implementation strategy 2019-02-12 10:43:46 +02:00
Laszlo Nagy c37b24d00f fmcadc5: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 4ec1204767 fmcadc4: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 51e35e081f fmcadc2: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 27f1e4eaed daq3: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 9b048f1a0e daq2: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy b98eb28dca adrv9371: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 3183fbf226 adrv9009: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy bed5ce516c adcfifo/dacfifo: fix alignments 2019-01-23 14:45:45 +02:00
Laszlo Nagy a3766b464b adcfifo/dacfifo: Use proc to create infrastructure
Create the dacfifo/adcfifo infrastructure with procedures.
This will allow moving the parameters of the dac/adcfifo inside
the block design so it can be calculated based on other parameters.
2019-01-23 14:45:45 +02:00
Laszlo Nagy e864786d3a adrv9371: use generic TPL
Use the generic TPLs for a better scalability to ease lane number
reductions.
2019-01-14 17:21:00 +02:00
Laszlo Nagy 0b66b39352 adrv9009/zc706: make SPI selection consistent 2018-12-21 17:32:48 +02:00
Laszlo Nagy 3d7a376f8b Makefile: update makefiles 2018-12-21 17:32:48 +02:00
Laszlo Nagy c9f1c92eaa adrv9009: use generic TPL
Make the block design parametrizable.
Limitations:
  F = 1,2,4
2018-12-21 17:32:48 +02:00
Laszlo Nagy 47093775ae adrv9009/zc706: top level cleanup 2018-12-21 17:32:48 +02:00
Laszlo Nagy 8adc285eab adrv9009/zc706: fix location constraints 2018-12-21 17:32:48 +02:00
Laszlo Nagy 7a5a8c5340 Revert "adrv9009: Removed ZC706 based project"
This reverts commit 7e7f75c0270bb6793bedb339f62b67bab9d77a6e.
2018-12-21 17:32:48 +02:00
AndreiGrozav f5af939c04 Add adi make(build) scripts
adi_make.tcl
  -adi_make::lib
  -adi_make::boot_bin (executes the script adi_make_boot_bin in xsct)
adi_make_boot_bin.tcl
2018-12-11 14:02:11 +02:00
Laszlo Nagy d8e11cfce5 daq2/3: update DAC TPL base addresses
The TPL for DACs can be relocated to addresses which match the software
expectations.
2018-12-04 14:02:22 +02:00
Adrian Costina e09f3290ff adrv9009: Move intel project to upack2/cpack2 2018-12-03 12:23:24 +00:00
Lars-Peter Clausen bf50916a3f motocon: Use new pack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen da50d682c5 ad6766evb: Use new pack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 9b919636ca fmcjesdadc1: Use new pack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Lars-Peter Clausen 1d223c19f8 fmcadc4: Use new pack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00