3c6c45962a
adrv9371x/kcu105: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
572005abe4
adrv9371x/zcu102: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
501903bc81
adrv9371x/zc706: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
39e073e6bf
adrv9371x: Use the output of IBUFDS_GTE2 as reference for the clock gens
...
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset. This will stop the clock generators from getting a clock prior
removing the reset of the XCVR. The XCVR has a requirement of running
user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
2022-02-15 11:09:37 +02:00
6a92bd5925
adrv9371x: Parameterize JESD204 configuration values
2022-01-12 16:05:48 +02:00
63b6711cfa
start adding some doc to the ./projects directory
...
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
2021-11-10 14:01:06 +02:00
58c1d2e3b2
projects: fixed xcvr clocks that generated critical warning
2021-11-09 12:40:14 +02:00
d4126739b4
projects: remove hardcoded div_clk from xcvr
2021-10-27 12:11:22 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
8343c03f5c
adrv9371x: remove IOB attribute from rx and rx_os
2021-07-26 12:42:21 +01:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
...
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
85f5dc8230
ad9371x/intel: Fix fPLL configuration
...
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
...
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
37254358dd
makefile: Regenerate make files
2020-10-20 12:51:10 +03:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
3241924d14
sysid_intel: Added sysid to intel projects
2020-09-11 15:46:06 +03:00
8818089015
a10soc: Reconfiguration interface address width improvement
...
The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
fb7da01498
adrv9371x/a10gx: Set optimization mode to aggressive performance
2020-08-17 10:43:03 +03:00
02ada3bbf7
a10gx: Delete input/output delay definitions
...
All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
a39fa831d0
ad9371:a10gx: Relax interconnect requirements
2020-08-11 10:14:18 +03:00
7e22f91429
adrv9371:a10gx: Remove constraint from DDR
2020-08-11 10:14:18 +03:00
47a97aac7c
adrv9371x/intel: Update project to use generic JESD204B TPL
2020-05-25 11:55:40 +03:00
32eeedb660
makefile: Update makefiles
2020-05-07 08:41:49 +01:00
e22016de4c
adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters
...
Update GTH3 parameters according to a 10Gbps link from the Transceiver
Wizard.
2019-10-08 10:38:46 +03:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
44deaadb4a
adrv9371: Add decimation and interpolation filters
2019-08-20 16:24:47 +03:00
36a1767329
Add generic fir filters processes for RF projects
2019-08-20 16:24:47 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
04ce10a570
cosmetics: Change Altera to Intel in comments
2019-06-29 06:53:51 +03:00
6e6f1347d7
project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl
2019-06-29 06:53:51 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
ec67a381e4
adi_project: Rename the process adi_project_altera to adi_project
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
019390f9bf
block_design: Updates with new reset net variables
2019-06-11 18:13:06 +03:00
9072779e41
adrv9371x: Clean out system_db.tcl
2019-06-11 18:13:06 +03:00
7960b00684
block_design: Update with new clock net variables
...
Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
70b7d69ff8
whitespace: Delete all trailing white spaces
2019-06-07 10:20:15 +03:00
f113f8f32f
ad9371x/common: Fix ad_xcvrcon proc call
...
The process ad_xcvrcon has a device_clk attribute which can be used to
connect a custom device clock to the XCVR. Fix the proc call so we can
simplify the block design script.
2019-05-29 10:27:16 +03:00
7afc9e77a2
adrv9371:qsys: use bundled AXIS interface
2019-05-16 13:27:19 +03:00
7f16f823ff
Revert "axi_dmac: add tlast to the axis interface for Intel"
...
This reverts commit e2c75c015f
2019-05-16 13:27:19 +03:00
d894c30c2d
Remove deprecated/unused parameters
...
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
2019-03-30 11:26:11 +02:00
b98eb28dca
adrv9371: update adcfifo/dacfifo
2019-01-23 14:45:45 +02:00
e864786d3a
adrv9371: use generic TPL
...
Use the generic TPLs for a better scalability to ease lane number
reductions.
2019-01-14 17:21:00 +02:00
aed8478d10
adrv9371x: Use new pack/unpack infrastructure
...
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
10deddd6d2
adrv9371/zcu102: Tune the differential swing of the TX lines
2018-10-04 14:37:02 +03:00
4ce153e6e1
all/system_top.v: loopback gpio lines
...
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
15863795e8
adrv9371x:kcu105: Performance_Retiming results the highest WNS
...
In default strategy we having a few path with small negative slack inside of
the MIG, due to the high UI clock (300MHz).
This new strategy solves this issue.
2018-08-23 18:41:48 +03:00
2293374307
adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs
...
The affected projects are:
- FMCADC2/VC707 - 16Mb
- FMCADC5/VC707 - 16Mb
- DAQ2/ZC706 - ADC@1GB and DAC@8Mb
- DAQ2/KC705 - ADC@4Mb and DAC@4Mb
- DAQ2/VC707 - ADC@8Mb and DAC@8Mb
- DAQ2/KCU105 - ADC@4Mb and DAC@4Mb
- DAQ2/ZCU102 - ADC@8Mb and DAC@8Mb
- DAQ3/ZC706 - ADC@1GB and DAC@8Mb
- DAQ3/KCU105 - ADC@4Mb and DAC@4Mb
- DAQ3/ZCU102 - ADC@8Mb and DAC@8Mb
- ADRV9371x/KCU105 - DAC@8Mb
- ADRV9371x/ZCU102 - DAC@16Mb
2018-08-21 11:44:05 +03:00
Laszlo Nagy
Filip Gherman
Robin Getz
LIacob106
Adrian Costina
Sergiu Arpadi
Istvan Csomortani
AndreiGrozav
Lars-Peter Clausen