664ef017bb
ad9361- ensm through dev-if
2015-08-27 11:41:52 -04:00
b0d22d323a
ad9361- axi-clock definitions
2015-08-26 14:11:43 -04:00
7780b3a3a2
2015.2 updates
2015-08-26 11:33:27 -04:00
7b858bc5ad
Revert commit 6b99ce
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Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
6b99ce2482
library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2
2015-08-20 18:17:38 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
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Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
6862655b0d
Add .gitattributes file
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Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
6338dfd8b7
ad9361: ip defaults & rst output
2015-06-05 09:19:39 -04:00
91b0f70972
library: remove drp cntrl
2015-06-02 09:58:57 -04:00
7c9bc40c75
axi_ad9361&TDD: Update TDD
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+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
2e7135c3c2
axi_ad9361_tdd: Initial commit.
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Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
e3b834ea02
axi_ad9361: Add CDC constraints
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Add proper constraints for all the CDC synchronizer paths to the axi_ad9361
core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 20:12:06 +02:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
e650253013
library: register map changes and for mathworks
2014-06-24 14:22:05 -04:00
842cd98b61
ad9361: adc loopback option
2014-05-27 12:15:02 -04:00
580808e146
axi_ad9361: added
2014-03-11 20:01:55 -04:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
Lars-Peter Clausen