f1168f9e29
fmcjesdadc1/a5gt- use xilinx setup 2-dma
2016-12-22 14:14:21 -05:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
da7f4608a8
fmcjesdadc1/usdrx1: Clean up the mess
...
Delete accidentally commited generated files.
2016-12-19 15:35:20 +00:00
8d799d0316
fmcjesdadc1: Intergrate ad_sysref_gen into project
2016-12-19 13:37:29 +00:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
45fd4f806d
fmcjesdadc1: Fixed RX_PMA_CFG parameter
2016-11-25 16:33:58 +02:00
daa3df4b96
projects/- xcvr updates
2016-11-22 16:23:05 -05:00
e62fe0c086
fmcjesdadc1- a5gt/a5soc- sysclk is different
2016-11-11 10:34:18 -05:00
85eac8c811
fmcjesdadc1/a5*- updates
2016-11-10 16:57:06 -05:00
7a2c713a4e
fmcjesdadc1/a5* - hdlmake.pl
2016-11-10 11:37:06 -05:00
c6730ab2d7
fmcjesdadc1/a5gt- updates
2016-11-10 11:36:41 -05:00
c207589f4b
fmcjesdadc1/a5gt - qsys2tcl flow
2016-11-10 11:32:29 -05:00
a54092c9bb
fmcjesdadc1: Update projects to xcvr framework
...
This commit contains modifications for Xilinx only
2016-11-10 10:59:52 +02:00
0b58a2a1db
avl_adxcvr- sysclk frequency
2016-11-09 09:21:07 -05:00
aef3e87d7e
fmcjesdadc1/a5soc -- xcvr frame work updates
2016-11-08 15:20:48 -05:00
53c2f0642b
fmcjesdadc1/a5soc -- xcvr frame work updates
2016-11-08 15:20:33 -05:00
acb9bf3902
hdlmake- a5soc/a5gt- updates
2016-11-04 15:02:57 -04:00
8ea9beffaf
fmcjesdadc1- a5soc tcl updates
2016-11-04 15:01:19 -04:00
905e29eb01
hdlmake- altera
2016-10-10 12:55:55 -04:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
b8c34791d5
version_upgrade: fmcjesdadc1 updated to 2016.2
...
Xilinx IP core JESD204 is updated to version 7.0
2016-09-06 11:41:37 +03:00
0b0aa8e6c0
Makefile: Add MMU option to altera makefiles
2016-08-11 17:46:54 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
f784557895
lib_refactoring: IOBUF is a Xilinx macro, no need to use with Altera
2016-08-08 15:06:34 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
eaf4d4a19d
makefile updates
2016-06-10 14:26:14 -04:00
be74db656c
ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1:
...
Update system_project.tcl scripts to correctly select the necessary
constraint files
2016-05-04 19:37:33 +03:00
21208ca208
Makefiles: Update Makefiles
2016-03-31 12:37:47 +03:00
59c726ecbe
fmcjesdadc1: Updated common design to 2015.4
2016-03-16 10:14:06 +02:00
89f7aadfb1
fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output
...
This will allow for the transceivers to be reset by the axi_jesd_xcvr core
2016-02-23 11:31:07 +02:00
0f37dd6424
fmcjesdadc1: Fixed project
...
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
61f9f72a75
fmcjesdadc1: Updated VC707 project for maximum throughput from DMA to DDR
...
- Increased the DMAs internal FIFO
2016-02-09 12:30:56 +02:00
c431adb793
fmcjesdadc1: Updated KC705 project for maximum throughput from DMA to DDR
...
- Increased the DMA internal FIFO
2016-02-09 12:00:27 +02:00
59fbd99fdb
fmcjesdadc1: Added clock constraint for the ADC path
2016-01-22 15:46:20 +02:00
2309c4d83c
Makefiles: Removed " from path
2015-11-27 14:02:46 +02:00
159f6c1216
Makefiles: Updated Makefiles
...
- for altera projects, taken into consideration of the new location for common qsys files
- for fmcomms5, added wfifo dependency
- for daq3, added mfifo dependency
2015-11-27 12:39:42 +02:00
e8a595b81e
fmcjesdadc1: Updated a5soc design
2015-11-24 15:39:52 +02:00
fd3910a915
fmcjesdadc1: Updated a5gt design
2015-11-24 15:39:21 +02:00
9281eb2c33
fmcjesdadc1: Updated common altera design
2015-11-24 15:38:58 +02:00
5cc97c78d3
Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries
2015-11-10 09:32:50 +02:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
7f9c526683
fmcjesdadc1: VC707 update project
2015-09-24 19:50:14 +03:00
78fe05120b
fmcjesdadc1: Updated KC705 project
2015-09-24 19:14:48 +03:00
70c7c2aeb8
fmcjesdadc1: Updated ZC706 project
2015-09-24 19:14:05 +03:00
2ed161628d
fmcjesdadc1: Updated project to 2015.2.1
...
- updated to the new jesd framework
- added cpack core
2015-09-24 19:12:40 +03:00
7e2255f4d9
fmcjesdadc1: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:05 +02:00
Rejeesh Kutty
Istvan Csomortani
Adrian Costina
AndreiGrozav
Lars-Peter Clausen