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6 Commits (f1e75963a2c91b40753d1af9746e1619c9cba754)

Author SHA1 Message Date
Istvan Csomortani 0613dca0b7 axi_dmac: Move the 'axis_xlast' logic into the dest_axi_stream module 2015-05-06 16:10:28 +03:00
Istvan Csomortani 65af205d6b axi_dmac: Add axis_last control signal to the Master AXI Streaming interface 
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
 2015-05-06 13:54:31 +03:00
Istvan Csomortani 0e1a60e8b7 axi_dmac: Brought up the transfer request signal for the dest_fifo and dest_axi_stream interface. 2015-03-26 12:20:32 +02:00
Lars-Peter Clausen e373b85954 axi_dmac: Fix Vivado warnings 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-18 20:59:13 +01:00
Lars-Peter Clausen f02ba999ae axi_dmac: Add support for DMA bus widths other than 64 bit 
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-13 13:20:10 +01:00
Adrian Costina 831c19ea84 Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00