2 Commits (f2060e27be66075f3adbd49f7c796ecefe32e9e6)

Author	SHA1	Message	Date
Laszlo Nagy	4b13274c55	ad9361/all/system_constr.xdc: remove manual clock definition ... Having a clock assigned manually to the clk output pin of the axi_ad9361 let the Vivado timing engine to not ignore the clock insertion delay when analyzing paths between clk_0 and the manually created clock that has the same source (clk_0), resulting in timing failure.	2019-04-12 10:48:50 +03:00
Istvan Csomortani	26822af7e1	adrv9361z7035: Rename pzsdr2 to adrv9361z7035	2017-05-25 17:17:54 +03:00