6 Commits (f2cd7626f58d1f8469d4ff58d0891250aaeafa4f)

Author	SHA1	Message	Date
Lars-Peter Clausen	41cc92ef49	Remove BASEADDR/HIGHADDR parameters ... This is unused and unneeded. The AXI interconnect will make sure that a peripheral only gets requests that are meant for it, there is no need to check the address in the peripheral itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2014-09-11 12:26:37 +02:00
Istvan Csomortani	f9a67371c0	Zynq Base System: Reset is synchronized to lowest system clock ... System reset (sys_100m_reset) is synchronized to lowest system clock (FCLK0), via a Processor System Reset module	2014-03-26 17:58:14 +02:00
Rejeesh Kutty	dc44703cf1	zynq/non-zynq: identical signal names and instances	2014-03-17 17:02:03 -04:00
Rejeesh Kutty	a6da4ca01c	zynq/non-zynq merge variables	2014-03-17 16:39:52 -04:00
Rejeesh Kutty	f3ae57a53e	global clock and reset names	2014-03-11 09:57:59 -04:00
Rejeesh Kutty	ddac1a8834	added common board files	2014-02-28 21:17:01 -05:00