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Author SHA1 Message Date
Istvan Csomortani d4200aee9a axi_pulse_gen_regmap: Rename the clk output to clk_out 2019-08-08 14:26:07 +03:00
Arpadi fe09acaa2f up_axi_update: ADDRESS_WIDTH parameter is now a localparam 
ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2;
up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
 2019-07-26 11:58:58 +03:00
Istvan Csomortani 0e7b38ebcf axi_pulse_gen: Initial commit 
The axi_pulse_gen is a generic PWM generator, which can be configured
through an AXI Memory Mapped interface.

The current register map look like follows:

  0x00 - VERSION
  0x04 - ID
  0x08 - SCRATCH
  0x0C - IDENTIFICATION - 0x504c5347 which stands for 'PLSG' in ASCII
  0x10 - CONFIGURATION - contains reset and load bits
  0x14 - PULSE_PERIOD
  0x18 - PULSE_WIDTH

Also update all the other modules, which instantiate the util_pulse_gen.
 2019-03-20 08:21:22 +00:00