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51 Commits (f41391fa937aa9ea2b36dde2b40dd5dbb3bcb4f1)

Author SHA1 Message Date
PopPaul2021 86836f5a40 library/common: Added DAC custom read/write interface in up_dac_common. 
The DAC common regmap was updated with 3 registers(rd/wr/ctrl) and 1 interface status flag for converters with custom control interface.
 2023-10-02 11:07:08 +03:00
AndreiGrozav 385e135561 axi_adrv9001: Change the DDS sync structure 
The DDS for each channel was synchronized by the main channel.
One problem with this aporoach is that when a user sets a DDS that
is not from the main channel the sinchronization does not happend.
This behavior is not user friendly in IIO-Oscilloscope or within other
configuration methods.

This commit keeps all channels in sync by triggering the sync on all
channels from each individual channel.
 2023-09-29 10:11:49 +03:00
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 15:22:26 +03:00
Iulia Moldovan 1cac2d82e1 Add copyright and license to .xdc files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 11:03:02 +03:00
Iulia Moldovan 27bb69b44c Add copyright and license to .sdc files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-25 10:41:40 +03:00
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-07-11 15:17:41 +03:00
Iulia Moldovan db94628cc6 library & projects: Update Makefiles 
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-01-27 11:54:05 +02:00
Iulia Moldovan a88215abc1 axi_adrv9001/intel: Add dummy parameter IODELAY_ENABLE in adrv9001_rx 
- Issue introduced by commit 173f4a83d4
 - When IODELAY_ENABLE was inserted in axi_adrv9001_if for adrv9001_rx (Xilinx instance),
   for Intel instance (intel/adrv9001_rx.v) was omitted and caused a build error for
   adrv9001/a10soc

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2023-01-18 14:52:30 +02:00
AndreiGrozav 22fbb05256 Update IPs based on up_adc_common changes 2023-01-12 13:09:35 +02:00
Iulia Moldovan 45346b1957 library: Cosmetic changes for modules that use ad_serdes_* 
Edited in:
 * axi_ad9122
 * axi_ad9434
 * axi_ad9684
 * axi_ad9739a
 * axi_ad9783
 * axi_adrv9001
 * ad_serdes_clk
 * ad_serdes_in
 * ad_serdes_out

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2022-12-15 14:22:40 +02:00
Iulia Moldovan 173f4a83d4 ad_serdes: Add features and update their instances in /library 
- ad_serdes_in:
  * Removed unused ports: loaden, phase, locked
  * Added IODELAY_ENABLE is set to be by default 1
  * Added conditional instantiation (using IODELAY_ENABLE) to IDELAY modules
  * Added conditional instantiation (using IODELAY_CTRL_ENABLED) to IDELAYCTRL module, based on IODELAY_ENABLE

- library: Update ad_serdes_in instances: add IODELAY_ENABLE
   * Edited in:
     * axi_ad9434
     * axi_ad9684
     * axi_adrv9001

- ad_serdes_out:
  * Removed unused port: loaden

- library: Update ad_serdes_out instances
   * Edited in:
     * axi_ad9122
     * axi_ad9739a
     * axi_ad9783
     * axi_adrv9001

- ad_serdes_clk:
  * Remove unused ports: loaden, phase

- library: Update ad_serdes_clk instances
   * Edited in:
     * axi_ad9122
     * axi_ad9434
     * axi_ad9684

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
 2022-12-15 14:22:40 +02:00
alin724 28ace647d1 up_adc_common: Update IPs and adi_regmap_adc definition file to latest up_adc_common module 2022-10-05 14:56:36 +03:00
alin724 775a23ebf2 up_adc_channel: Update IPs and adi_regmap_adc definition file to latest up_adc_channel module 2022-10-05 14:27:51 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file 
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
 2022-08-08 13:52:54 +03:00
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline 
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 2022-06-28 18:06:56 +03:00
Iulia Moldovan d9ec44657f libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
Nick Pillitteri c1721e18dd account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores 2022-03-24 16:29:49 +02:00
Laszlo Nagy e66c5282bc axi_adrv9001: Expose IODELAY_CTRL parameter to top level 2022-03-02 11:06:12 +02:00
AndreiGrozav c2d960e029 axi_adrv9001: Add external sync support 
The external sync must be synchronous to the reference clock, in order
to obtain a deterministic synchronization of the interface.
 2021-12-16 15:16:30 +02:00
Laszlo Nagy 41525f348b axi_adrv9001/axi_adrv9001_core.v: Disable TDD and IOCTRL if second SSI interface is disabled 2021-12-08 17:31:53 +02:00
Laszlo Nagy dfe153dc68 axi_adrv9001/axi_adrv9001_tdd.v: Add disable option for TDD 2021-12-08 17:31:53 +02:00
Laszlo Nagy 8cc0367e8f axi_adrv9001: Hide disabled interfaces 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-12-08 17:31:53 +02:00
Laszlo Nagy 6a4b46ebb4 axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional 
If the Rx2 and Tx2 SSI are disabled the rx1,tx2 data paths are forced to
R1 mode.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-12-08 17:31:53 +02:00
Laszlo Nagy b25c37a8cc axi_adrv9001/intel: Add dummy parameters to match Xilinx interface 
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
 2021-11-12 14:09:14 +02:00
Laszlo Nagy fcb16daf5b axi_adrv9001: Add the option of global clock buffers on 7 series 
Using global clock can help placement issues where the logic does not fits in one
clock region.
 2021-11-08 13:53:51 +02:00
Laszlo Nagy d493b724f2 axi_adrv9001/adrv9001_rx.v: Simplify clocking 2021-10-27 14:40:08 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
LIacob106 16a93a804b adrv9001[intel]: Add second pair of DMAs 
fix observations for PR
 2021-09-01 15:04:14 +03:00
alin724 f8c82c611d axi_adrv9001: Add support for symbol operation mode on Xilinx devices 
Add CMOS support for the interface for the following symbol modes on Xilinx devices:

A              B  C       D                     E       F      G            H
CSSI__1-lane   1  16/8    80(SDR)/160(DDR)      80      -      SDR/DDR      SDR/DDR->4/2(C=16), 2/1(C=8)

Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate

CSSI - CMOS Source Synchronous Interface
 2021-08-17 15:33:06 +03:00
stefan.raus 1f24344620 Update Quartus version to 20.4 
Update quartus compilation tools from 20.1 to 20.4.
Remove hardcoded version from axi_adrv9001 ip.
 2021-08-12 11:15:01 +03:00
Josh Blum e1829a061d adrv9001: fixes for reset metastability on xilinx ioserdes 
* fixes DRC warning that the clocking configuration may result in data errors
* fixes ioserdes reset issue with synchronous de-assert in data clock domain
 2021-07-09 11:11:04 +03:00
Laszlo Nagy aa180fb272 axi_adrv9001: Let gate signals have initial value, useful for simulation 2021-05-26 15:44:45 +03:00
Laszlo Nagy b85784ebe8 axi_adrv9001: rx: calculate ramp value based on received value 2021-05-26 15:44:45 +03:00
Laszlo Nagy 9a93b56882 axi_adrv9001:rx: Add reset to link layer 
Fix random valid signals after resets on the Rx interface.
 2021-05-26 15:44:45 +03:00
Laszlo Nagy 4c35af74d4 axi_adrv9001:rx:phy: do not generate valid while in reset 2021-05-26 15:44:45 +03:00
Laszlo Nagy 32dbde6945 axi_adrv9001: Allow running Rx2/Tx2 channels in R1 mode without Rx1/Tx1 
This commit removes the deadlock created while trying to use the Rx2/Tx2
channels without the Rx1/Tx1 channels enabled first.
 2021-05-26 15:44:45 +03:00
Laszlo Nagy 08b0d19731 axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks 
Depending on FPGA technology the physical layer uses different
deserialization factors and corresponding clock division factors to
divide the source synchronous interface clock. This must be
exposed to software so it can act on it while setting the DDS rate.

Xilinx CMOS clock ratio - 4
Xilinx LVDS clock ratio - 4
Intel  CMOS clock ratio - 1
 2021-05-26 15:44:45 +03:00
Laszlo Nagy c718ba91f1 axi_adrv9001: Add status bit for Tx clocking 
If Tx source synchronous clock is not routed through clock capable pins
the interface and driving logic must run on the Rx interface clock.
This introduces a dependency, Rx interface must be bring up before the
Tx. In this mode a Tx only operation is not possible.

This is done through a synthesis parameter.
Expose this parameter to the software so it can query if the limitations
exists in the implementation.
 2021-03-17 16:34:12 +02:00
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0 
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
 2021-03-08 11:29:33 +02:00
Laszlo Nagy 85729def2a axi_adrv9001: Double sync control lines between interface 1 and 2 2021-03-04 11:13:10 +02:00
Laszlo Nagy 50c4c3e815 axi_adrv9001: Fix channel 3 for Tx1 in DMA mode 2021-03-04 11:13:10 +02:00
Laszlo Nagy 3aa8a631d0 axi_adrv9001: Quartus 19.3 updates 2021-03-04 11:13:10 +02:00
Laszlo Nagy 714d557245 axi_adrv9001: Add opt-in synthesis parameters 2021-01-26 15:22:41 +02:00
Laszlo Nagy 31929167d3 axi_adrv9001: Use global clocks for divided down clock 2021-01-26 15:22:41 +02:00
Laszlo Nagy c7046a6d72 axi_adrv9001:axi_adrv9001_rx_channel: fix ramp signal checking 2021-01-26 15:22:41 +02:00
Laszlo Nagy 54c2cf7d12 ad_tdd_control: Fix rx/tx only behavior 
When tx_only disable rx_enable and vice-versa
 2021-01-20 13:00:01 +02:00
Laszlo Nagy 58f2eec127 axi_adrv9001: Export TDD mode 2021-01-20 13:00:01 +02:00
Laszlo Nagy afa3f11206 axi_adrv9001: Add TDD support 2021-01-20 13:00:01 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00