Commit Graph

3446 Commits (f41391fa937aa9ea2b36dde2b40dd5dbb3bcb4f1)

Author SHA1 Message Date
StancaPop 17d3baf417 ad7616_sdz: Add axi_clkgen 2023-11-09 14:43:20 +02:00
Stanca Pop f1f3968485 ad7616_sdz: Remove zc706 support 2023-11-09 14:43:20 +02:00
Stanca Pop 3446cc2100 ad7616_sdz: Add fmc pinout 2023-11-09 14:43:20 +02:00
Stanca Pop d97550fa71 ad7616_sdz: Use SPI Engine for serial mode
This commit makes the following changes:
Add SPI Engine for serial mode
Add SER_PAR_N build parameter, set default 1 for serial
Fix irq consistency in ad7616_bd.tcl
Fix regmap and offload names
Fix system_top.v GPIOs
2023-11-09 14:43:20 +02:00
PIoandan a806a6f6ec
projects: Add missing sysid IP (#1172)
* Projects: Add missing sysid IP

* Added make parameters for the sysid ip for the projects: ad9209_fmca_ebz/vck190, ad9213_dual_ebz/s10soc and adrv9009/s10soc

Signed-off-by: Pop Ioan Daniel <pop.ioan-daniel@analog.com>
2023-11-03 09:52:13 +02:00
kylex 365933542d
scripts/adi_board.tcl: use axi_interconnect for HP ports on Zynq-7000 family
Commit 5db7574 switched ad_cpu_interconnect from SmartConnect to
AXI Interconnect for Zynq-7000 family SoC. This commit does the
same for ad_mem_hpx_interconnect.

Signed-off-by: Alexander Vickberg <wickbergster@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-10-30 09:48:32 -03:00
Iulia Moldovan f81532d1d7 projects: Update Readme.md for ad9783_ebz & ad9081/ad9082_fmca_ebz
* Now the Readme.md points to the GitHubIO documentation

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-10-26 09:13:36 +03:00
PIoandan daf9e1744a
pulsar_adc_pmdz: Add .txt file for constraints
I changed the comments from  system_constr.xdc file.
Added pulsar_adc_pmdz_pmod.txt.
Tests were done on the eval-ad7689-ebz and eval-ad7984-pmdz boards.

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2023-10-25 17:15:23 +03:00
PIoandan 86216958a7
Update cn0363 spi engine (#1183)
* Update cn0363 spi engine

I replaced the SPI Engine connections in the cn0363_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I updated the system_constr.xdc file and
created the cn0363_pmod.txt file.

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2023-10-25 15:26:36 +03:00
Bogdan Luncan b1002cacbe common: vmk180: Connected missing ss from spi
ad9081_fmca_ebz: vck190: system_top: Fixed spi signals indentation

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2023-10-25 13:13:01 +03:00
PIoandan d3be77931b
Update ad469x spi engine (#1181)
* Update ad469x spi engine

I replaced the SPI Engine connections in the ad469x_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I also created the ad469x_fmc.txt file for generating the
system_constr.xdc file.

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2023-10-24 12:44:48 +03:00
PIoandan 18cb0b7846
Update ad738x spi engine (#1179)
* Update SPI Engine AD738x

I replaced the SPI Engine connections in the ad738x_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I changed the ad738x_bd.tcl where it was added spi_engine_create
procedure, system_bd.tcl and system_top.v files.
I have update system_constr.xdc file and added ad738x_fmc.txt file.

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2023-10-24 12:06:06 +03:00
Ioan-daniel Pop 219680968e V2: Update ad5766 spi engine
I edited the ad5766_fmc.txt file.

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2023-10-24 10:36:07 +03:00
Ioan-daniel Pop 8dbdfcce37 Update ad5766 spi engine
In this project it was created the ad5766_fmc.txt file for generating the system_constr.xdc file.
Also it was updated the system_constr.xdc and Readme.md files.

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2023-10-24 10:36:07 +03:00
Ioan-daniel Pop db1ef483a4 V2: Update adaq7980 spi engine
Regenerated the Makefile.

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
2023-10-24 10:29:45 +03:00
Ioan-daniel Pop fce0491ad7 Update adaq7980 spi engine
I replaced the SPI Engine connections in the adaq7980_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I configured the parameters for axi_pwm_gen and axi_clkgen according
to the results in the SPI_Engine_Timing_Computations Excel where I created a file
for adaq7980.
I created the adaq7980_fmc.txt file for generating the system_constr.xdc file.
I modified the system_bd.tcl, system_top.v, system_constr.xdc and Readme.md files.
Also I regenerated the Makefile.
2023-10-24 10:29:45 +03:00
laurentiu_popa 7ccc505950 projects/ad7134_fmc: Add FMC pinout description
* Added txt description of all FMC pins used/unused
* Updated constraint files with FMC pinout location

Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
2023-10-19 13:56:12 +03:00
laurentiu_popa cf4d2b5a6f projects/ad4134_fmc: Add FMC pinout descripton
* Added txt description of all FMC pins used/unused
* Updated constraint files with FMC pinout location

Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
2023-10-19 13:55:30 +03:00
laurentiu_popa 497a5f3f3a projects/cn0561: Add FMC pin descripton for all carriers
* Added txt description of all FMC pins used/unused
* Updated constraint files with FMC pinout location

Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
2023-10-18 13:48:53 +03:00
Vilmos-Csaba Jozsa 16db583643
FMC pinout configurations for AD4630. (#1193)
* projects/ad4630_fmc: Added ad4630_fmc.txt FMC conf file and pinout comments for .xdc files.

Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
2023-10-18 10:28:11 +03:00
Liviu.Iacob 6e3553ef4f ad9083_evb/a10soc: Overwrite spi frequency 2023-10-17 10:13:45 +03:00
Ionut Podgoreanu 455bfbcafb pluto: Enable phaser integration
This commit adds support for ADALM-PHASER, allowing the user to choose between the default PlutoSDR mode and Phaser mode
through a software controlled GPIO pin: phaser_enable.

The Generic TDD Engine was integrated to output a logic signal on the L10P pin, which connects to the input of the ADF4159,
when receiving an external synchronization signal on the L12N pin from the Raspberry Pi. Two additional TDD channels are used
to synchronize the TX/RX DMA transfer start:
- TDD CH1 is connected to the RX DMA, triggering the synchronization flag;
- TDD CH2 is connected to the TX unpacker's reset, backpressuring the TX DMA until deasserted.

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-10-06 14:20:22 +03:00
AndreiGrozav cde9956948 ad4858_fmcz: Initial design
Reference design for AD4858 20-bit, low noise 8-channel, SAR ADC with
buffered differential, wide common range picoamp inputs.

The design supports:
- CMOS and LVDS interfaces(at build time)
- Runtime sampling changes
- Store captured samples in RAM, through DMA (available via software support)

Documentation at: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
2023-10-05 10:19:03 +03:00
PopPaul2021 c29c092bdc projects/ad3552r_evb: Added project for AD3552R-EVB on ZedBoard.
The project controls the AD3552R digital-to-analog converter and transmits data written in the DDR memory to the QSPI interface of the DAC.
The reference clock is generated by an axi_clkgen IP and is configured to output a 133MHz signal.
If both channels are enabled and data streaming is DDR the sample rate is 16.65MSPS.
If just one channel is enabled and data streaming is DDR the sample rate is 33.3MSPS.
The VADJ voltage should be set to 1.8V.

Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
2023-10-02 11:07:08 +03:00
Jem Geronimo 4abb8b3b97 dc2677a: add initial design
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
2023-10-02 15:10:04 +08:00
AndreiGrozav 8b07dfa033 jupiter_sdr: USB power delivery always on 2023-09-29 10:11:49 +03:00
AndreiGrozav 0b61df7847 jupiter_sdr: Change the SD ctrl config to autodir 2023-09-29 10:11:49 +03:00
AndreiGrozav 25aa1081aa jupiter_sdr: PL sysmon updates
Monitor VCC through VUSER1.
Disconnect the default redundant monitors.
Connect the pl_sysmon interrupt.
2023-09-29 10:11:49 +03:00
PopPaul2021 f5184b4e14 projects/cn0501: Removed CN0501 project.
The CN0501 project was removed because the board development was
canceled.

Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
2023-09-21 09:00:57 +03:00
Jem Geronimo 91ec36f417
projects/scripts/project-intel.mk: change 'system_top.v' to '$(wildcard system_top*.v)' (#1169)
Change necessary to build intel projects with different system_top verilog files.
This was patterned to ae09b8a1bb/projects/scripts/project-xilinx.mk (L70)

Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
2023-09-07 15:52:04 +08:00
AndreiGrozav 49cf0f7ae3 project-xilinx: Update the generic dependency list
The generic project dependency list contains:
system_top*.v
system_bd.tcl
system_project.tcl
system_constr.xdc
This items will not be included in the auto generated makefiles. But
used as generic dependency.

This commit adds:
-wildcard check of system_constr*.xdc.
-wildcard check of system_constr*.tcl.
2023-09-07 10:44:10 +03:00
alin724 c8a131ec0a ad7606x: Add dynamic configuration for AD7606X operation modes
AD7606x operation mode configuration:
REG_CNTRL_3
bit 8 - 'b1 - set operation mode indicated in bits [7:0];
bit [7:0] - set desired operation mode: 0 - SIMPLE, 1 - CRC, 2 - STATUS_HEADER, 3 - CRC_STATUS
2023-09-06 17:09:22 +03:00
ladace ae09b8a1bb
cn0561: Fixed critical warning during make (#1159)
The busy_sync pulse was replaced by an axi pwm generator IP, so the
constraint in xdc file is no longer needed.
2023-08-22 12:17:17 +03:00
AndrDragomir e42877d337 scripts/adi_fmc_constr_generator: Fix intel constr generation
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2023-08-14 18:05:02 +03:00
AndrDragomir fa2d520bf0 ad9213_evb: Add design
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2023-08-14 17:58:37 +03:00
Filip Gherman fc2437a83a ad9213_evb: Initial commit
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2023-08-14 17:58:37 +03:00
laurentiu_popa 8d0b6ba486 projects: Update incomplete/inaccurate readmes
Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
2023-07-31 09:35:39 +03:00
laurent-19 b03d985e9d projects: Update readmes all projects initial version
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-07-31 09:35:39 +03:00
laurentiu_popa e8b583802a projects: Update readmes initial commit
Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
2023-07-31 09:35:39 +03:00
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
Iulia Moldovan 1cac2d82e1 Add copyright and license to .xdc files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 11:03:02 +03:00
Iulia Moldovan 27bb69b44c Add copyright and license to .sdc files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 10:41:40 +03:00
Alin-Tudor Sferle a031cba1d5 project_xilinx.tcl: Fix the regex expression for Kria KV260 evaluation board 2023-07-19 11:32:10 +03:00
Iulia Moldovan 86c9847c5f Add copyright & license to .sh, .yml, .pl files. Edit Makefile for KV260
* Updated the Makefile for KV260 template as the copyright was not generated
   properly

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 18:39:55 +03:00
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
AndreiGrozav 8b15d66302 Rename pluto_ng to jupiter_sdr plus RevB updates
Update license according to the latest format
2023-06-30 09:14:07 +03:00
Bogdan Luncan 3f0a487b2e ad9082/vck190: Add initial design
ADC Mode 27: L=8, M=4, S=4, NP=12, LaneRate=24.75 GSPS
DAC Mode 35: L=8, M=4, S=4, NP=12, LaneRate=24.75 GSPS

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2023-05-16 12:13:55 +03:00
Bogdan Luncan 80fe536863 ad9081/vck190/system_project: Change the default profile
ADC Mode 26: L=8, M=8, S=2, NP=12, LaneRate=24.75 GSPS
DAC Mode 24: L=8, M=8, S=2, NP=12, LaneRate=24.75 GSPS

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2023-05-16 12:13:55 +03:00
Bogdan Luncan 294b681196 ad9081: Proper reset sequence for versal transceivers
- Removes the reset_tx_pll_and_datapath_in reset
- Connects gtreset_in to make use of the master reset found inside
the Transceiver Bridge IP
- Connects the necessary signals for the master reset between the
Transceiver Wizard and Transceiver Bridge

ad9209/vck190/system_top: Connect versal transceiver reset

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2023-05-16 12:13:55 +03:00
alin724 e530b3feec adrv9001_zcu102: Reduce allowed clock skew for rx*_dclkout in lvds_constr.xdc 2023-05-15 11:41:56 +03:00