Commit Graph

5 Commits (f41391fa937aa9ea2b36dde2b40dd5dbb3bcb4f1)

Author SHA1 Message Date
Ionut Podgoreanu 455bfbcafb pluto: Enable phaser integration
This commit adds support for ADALM-PHASER, allowing the user to choose between the default PlutoSDR mode and Phaser mode
through a software controlled GPIO pin: phaser_enable.

The Generic TDD Engine was integrated to output a logic signal on the L10P pin, which connects to the input of the ADF4159,
when receiving an external synchronization signal on the L12N pin from the Raspberry Pi. Two additional TDD channels are used
to synchronize the TX/RX DMA transfer start:
- TDD CH1 is connected to the RX DMA, triggering the synchronization flag;
- TDD CH2 is connected to the TX unpacker's reset, backpressuring the TX DMA until deasserted.

Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
2023-10-06 14:20:22 +03:00
Iulia Moldovan 1cac2d82e1 Add copyright and license to .xdc files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 11:03:02 +03:00
AndreiGrozav f9c8ff26cf pluto rev C hardware updates
-connect axi_spi to board GPIOs
-connect axi IIC to board GPIOs

MIO49 SPI_CS   (PS MIO49)
L10P  SPI_MOSI (AXI_SPI)
L12N  SPI_MISO (AXI_SPI)
L24N  SPI_CLK  (AXI_SPI)
L7N   iic_sda  (AXI_IIC)
L9N   iic_scl  (AXI_IIC)
2020-01-16 11:40:28 +02:00
Laszlo Nagy 0261eade0c zynq:all: fix SPI clock constraint
According to data sheets the EMIO SPI controller maximum frequency is
just 25MHz. Constrain the SPI clock accordingly.
2019-08-09 16:39:56 +03:00
Rejeesh Kutty 2ececad58c sdrstk-2-pluto 2016-11-11 13:49:04 -05:00