Change necessary to build intel projects with different system_top verilog files.
This was patterned to ae09b8a1bb/projects/scripts/project-xilinx.mk (L70)
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
The generic project dependency list contains:
system_top*.v
system_bd.tcl
system_project.tcl
system_constr.xdc
This items will not be included in the auto generated makefiles. But
used as generic dependency.
This commit adds:
-wildcard check of system_constr*.xdc.
-wildcard check of system_constr*.tcl.
The ADI_EXTRACT_PORTS variable is used to extract all the ports and nets properties of the desired IPS for the TransceiverToolbox and HighSpeedConverterToolbox to be later used for generating the json files automatically.
The ADI_SKIP_SYNTHESIS variable is used to stop the building process before the synthesis when used with Matlab support as it is not necessary at this point.
The ADI_MATLAB variable is used to choose the correct paths when building the design when using the HWA workflow.
bug:
say "make LVDS_CMOS_N=0"
- will set ad_project_dir as LVDSCMOSN0
- will then set system_qip_file as LVDSCMOSN0/system_bd/synthesis/system_bd.qip
- build error reveals system_bd can't be found
- maybe due to setting ad_project_dir as a relative file path
fix:
- set ad_project_dir as an absolute file path
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.
Note that the 'JESD' and 'LANE' words from the parameter names are stripped.
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
In ad_xcvrcon procedure from adi_board, phy_en_char_align must be connected only when 8B10B encoding is used,
otherwise this signal does not exists in the JESD ip and will cause an error.
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
Using the script:
- make sure that the eval board in use has a common fmc connection file.
if you created a new one, it should be saved as &project_name_fmc.txt inside
&project_name/common
- open a tcl terminal, either inside or outside the project
- make sure your current directory is &hdl_repo/projects/&project_name/&carrier
- source the script found at &hdl_repo/project/scripts/fmc_constr_generator.tcl
- call gen_fmc_constr $parameter_1 $parameter_2:
- in case of only one fmc port on the carrier call without any parameters
- if there are two fmc ports on the carrier and you want to use only one,
the first parameter should contain an indication (fmc_lpc/hpc, fmc0/1, etc.)
- if there are two fmc ports on the carrier and you want to use both, then
both parameters should contain an indication
- the constraints file will be generated in the current directory
Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
For some newer versions of git where by default color.ui=always.
The colored string captured can result in some special characters
(ASCI escape codes for coloring the terminal output) before and after the string.
e.g:
$ git branch > test.txt
$ vim test.txt
"
* ^[[32mmaster^[[m
dev_new_device^[[m"
The above escape codes will mess up a terminals color scheme when this
information is read from sysid and displayed on a terminal.
Use --no-color flag to fix this issue.
New version of Quartus Standard for de10nano and sockit was changed
to 21.1.
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
New version of Quartus Pro for A10SOC, A10GX and S10SOC was changed
to 21.4. Is known that some projects will not build anymore due to
timming violations.
- allow specifying the name of Axi Lite interface from the peripheral were to connect the control bus
- some DDR controllers have an Axi Lite control interface, this creates
a second address segment which causes issues, differentiate the memory
segment from control registers segment
The 2020.1 Xilinx tools have a different tcl procedures to build the boot.bin
file.
This commit updates the adi_make tcl flow for the new tools. The new
process is not backwards compatible with tools older than 2020 version.
In order to workaround optimization issues hit in Vivado 2020.2,
set ADI_USE_OOC_SYTHESIS variable by default to 1. This will build
projects in Out Of Context mode.
Projects can be build in Project Mode by exporting ADI_USE_OOC_SYTHESIS=n.
Update vivado version to 2020.2:
- update default vivado version from 2020.1 to 2020.2
- add conditions to apply specific contraints only in Out Of Context mode.
- update DDR controler parameters for vcu118 and kcu105 dev boards
Jem Geronimo
AndreiGrozav
AndrDragomir
Iulia Moldovan
Alin-Tudor Sferle
Stanca Pop
Istvan-Zsolt Szekely
LIacob106
Bogdan Luncan
Filip Gherman
ladace
Morten Jensen
Laszlo Nagy
hotoleanudan
Adrian Costina
stefan.raus
Robin Getz
sergiu arpadi
David Winter