7 Commits (f57643b45113f1282b75623431bf744fc92b2b3d)

Author	SHA1	Message	Date
Istvan Csomortani	a66029aef3	adrv9009/a10gx: Delete redundant timing constraints	2020-08-11 10:14:18 +03:00
Istvan Csomortani	02ada3bbf7	a10gx: Delete input/output delay definitions ... All input and output delays should be referenced to a virtual clock. If the input and output delays reference base clocks or PLL clocks rather than virtual clocks, the intra- and inter-clock transfer clock uncertainties, determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports. See mnl_timequest_cookbook.pdf for more info.	2020-08-11 10:14:18 +03:00
Istvan Csomortani	6e6f1347d7	project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl	2019-06-29 06:53:51 +03:00
Istvan Csomortani	79b6ba29ce	all: Rename altera to intel	2019-06-29 06:53:51 +03:00
Laszlo Nagy	3183fbf226	adrv9009: update adcfifo/dacfifo	2019-01-23 14:45:45 +02:00
Adrian Costina	e09f3290ff	adrv9009: Move intel project to upack2/cpack2	2018-12-03 12:23:24 +00:00
Adrian Costina	401395cdd1	adrv9009: A10GX: Initial commit	2018-11-27 15:31:21 +02:00