f26c1de38a
ad9361/xilinx/lvds_if- fix frame check
2017-07-25 16:37:01 -04:00
3eeba8273a
hdlmake.pl/fmcomms2- updates
2017-07-24 16:33:40 -04:00
ff50963c7f
axi_ad9361- altera/xilinx reconcile- may be broken- do not use
2017-07-24 16:28:50 -04:00
206ea1f70a
ad9361/xilinx- missing up_rstn
2017-07-24 15:52:00 +01:00
247e540cf0
hdl/library- fix syntax errors/synthesis warnings
2017-07-24 15:31:22 +01:00
bc4526cc8a
axi_ad9361/altera- add 10 support
2017-07-21 10:33:44 -04:00
9b26763e3b
ad9361/xilinx- missing up_rstn
2017-07-21 09:08:28 -04:00
d132ed45cd
arradio- timing violations fix
2017-07-20 15:08:21 -04:00
6c986d9b6a
hdl/library- fix syntax errors/synthesis warnings
2017-07-20 14:07:32 -04:00
a63e268d6e
arradio/c5soc- interface updates
2017-07-20 13:05:07 -04:00
fca88caf93
arradio/c5soc- interface updates
2017-07-20 13:05:07 -04:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
ff037c0286
altera 16.1 ip changes
2017-05-26 10:48:00 -04:00
097924b95d
altera 16.1 ip changes
2017-05-26 10:46:28 -04:00
10898d6618
constraints: Split the regmap CDC constraint into separate file
2017-05-25 15:12:16 +03:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
c728299e71
altera- default to latest version
2017-05-12 13:25:17 -04:00
e4ae391237
axi adc cores: Add missing ports to up_adc_common instance
2017-05-12 13:39:05 +03:00
0e1e507541
axi dac cores: Add missing ports to up_dac_common instance
2017-05-12 13:37:34 +03:00
fea6eb68be
up_adc_common- port name changes
2017-05-10 14:45:17 -04:00
85a647eda8
axi_ad9361: Fix ad_cmos_out instantiations
...
This is a patch for 3627b89
2017-04-26 10:39:54 +03:00
52305f74c8
altera/ad_cmos_in|out: Delete redundant parameter
2017-04-25 12:06:33 +03:00
3627b892c3
xilinx/ad_cmos_in|out: Delete redundant parameter
...
The LVCMOS standard is a single ended IO standard. The SINGLE_ENDED
parameter is redundant in this case.
2017-04-25 11:02:35 +03:00
db0cd63ed3
axi_ad9361: Fix Warning[Synth 8-2611]
...
In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
2017-04-19 13:52:13 +03:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
c46989e4e8
Makefile: Update Makefiles for libraries
2017-03-30 18:33:22 +03:00
31a5c674f2
fmcomms2: Update constraints file paths
2017-03-30 16:16:02 +03:00
ea7e93d27f
fmcomms2: Use the new constriants from 335fef0
2017-03-29 18:36:09 +03:00
1ef064ac03
axi_ad9361- add receive init delay
2017-03-13 16:28:38 -04:00
0ae79ca7ac
move/rename - delay script belongs to ad9361
2017-03-10 12:44:32 -05:00
6b90054343
axi_ad9361: Define CDC constraint for tdd_sync
2017-02-24 11:24:07 +02:00
94bda1d415
axi_ad9361: Preserve 1bit CDCs with ASYNC_REG true
2017-02-23 11:43:10 +02:00
2b354af876
axi_ad9361_tdd: Register the tdd_sync_cntr output
2017-02-23 11:31:23 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
9d6c93a5d8
Fix warnings
2016-11-14 15:17:15 +02:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
9f4c5f8060
arradio/ad9361- updates
2016-10-31 15:34:32 -04:00
b94cc8afb1
altera- cmos cores
2016-10-31 13:13:48 -04:00
cc75fa3dfe
altera- java/tcl mess handling
2016-10-31 10:54:07 -04:00
a9d03af771
altera- serdes changes
2016-10-28 14:09:18 -04:00
08cef5a745
axi_ad9361: Add Cyclone V SERDES support
2016-10-25 20:24:17 +03:00
1131be91ed
axi_ad9361: Makefile update
2016-10-11 23:34:13 +03:00
b7767aa18f
xilinx/axi_ad9361_lvds_if: Remove ila
2016-10-11 18:13:45 +03:00
369dad60b0
axi_ad9361: Add Altera SERDES interface support
2016-10-11 17:59:19 +03:00
52194f0fea
axi_ad9361: Add DRP connection to the interface module
2016-10-11 17:59:12 +03:00
7194d2eccc
axi_ad9361: Grup interfaces to add support for more carriers
2016-10-11 17:58:49 +03:00
1b9d2d434c
axi_ad9361_tdd: Delete unused register
2016-10-05 17:41:08 +03:00
43b3761b80
axi_ad9361: Flop the tx and rx valid
2016-10-03 12:24:04 +03:00
b4fac96aad
axi_ad9361- independent disables
2016-09-28 15:45:27 -04:00
f7fb3ccaca
axi_ad9361: Change the data path gating
...
Bring up the datapath gating from the TDD controller module.
2016-09-28 16:36:13 +03:00
1a11e28821
ad9361- dac data path split
2016-09-23 16:13:46 -04:00
7be6168b2e
ad9361- adc data path split
2016-09-23 13:42:14 -04:00
78f7384150
ad9361- vivado synthesis warnings fix
2016-09-22 13:41:18 -04:00
913eafed48
up_drp : Update the DRP interface to support Altera platforms
2016-09-21 15:00:45 +03:00
2159f78c80
axi_ad9361: Delete invalid assignment of a generated wire
2016-09-16 17:38:08 +03:00
a183e51a12
axi_ad9361: Add parameter R1_MODE_EN
...
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
2016-09-09 16:34:11 +03:00
e42206e510
axi_ad9361: Add a TDD enable/disable parameter
2016-09-09 14:38:28 +03:00
be41a8bcaa
axi_ad9361: Delete debug ports of the tdd module
2016-09-09 14:38:28 +03:00
9799599eee
library/ad9361- add dac clk sel
2016-08-26 10:31:00 -04:00
6a8ca8107a
common: Added common ad_dcfilter stub for altera.
2016-08-16 17:37:16 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
aad8c265bc
lib_refactoring: Fix path for CMOS sources
2016-08-08 15:07:54 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
58b220ba81
ad_tdd_control: Add an on/off switch to the receive datapath
...
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
2016-08-01 11:49:27 +03:00
7485d27d37
ad9361/altera- device-family variable
2016-06-14 12:28:13 -04:00
5d437083cc
ad9361/altera- a10+ only
2016-06-14 12:19:54 -04:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
a262eb7ab3
ad9361- output-rst - associated-rst issue?
2016-05-18 13:24:13 -04:00
d7f0bd1b76
ad9361- add reset sink
2016-05-18 13:24:13 -04:00
bb4ed42a93
ad9361- add missing wires
2016-05-18 13:24:13 -04:00
68329de738
ad9361- interface updates
2016-05-16 12:19:38 -04:00
3871d3ce2b
ad9361-c5/a10 - updates
2016-05-09 13:54:08 -04:00
bdfa383622
library/axi_ad9361: tdd false paths
2016-05-04 13:42:12 -04:00
ef6c99ecab
library/axi_ad9361: hw component updates
2016-05-04 13:42:12 -04:00
3b5e44e37d
library/axi_ad9361: mmcm rst for plls
2016-05-04 13:42:12 -04:00
16a13b2023
library/axi_ad9361: add rst/locked to clock
2016-05-04 13:42:11 -04:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
3f5e1e1203
ad9361- dev_if module name change
2016-04-29 10:17:35 -04:00
243d3e6e41
ad9361- a10soc sdc files
2016-04-29 10:17:35 -04:00
aa2aa902bf
ad9361- a10soc updates
2016-04-29 10:17:35 -04:00
f411d29e30
ad9361- a10soc changes
2016-04-29 10:17:35 -04:00
779d014750
ad9361-common alt/xil interface
2016-04-29 10:17:35 -04:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
583ef82fd0
ad9361- cmos mode
2016-03-04 10:39:48 -05:00
7d2939be92
ad9361- cmos mode initial commit
2016-03-04 10:39:48 -05:00
a747fad540
axi_ad9361: tx_valid must be controlled by the TDD controller
2016-02-12 14:33:34 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
...
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
12c95b059d
ad_tdd_control: Remove tdd_enable_synced control line
...
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
275ec3d3a8
axi_ad9361: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:21:08 +02:00
250f3c917b
axi_ad9361: Removed old signals from the altera device interface module
2015-11-24 11:20:35 +02:00
fc0f4bc414
axi_ad9361: Delete the old sync generator from the core
...
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
c03983ca54
ad_tdd_sync/control: Update TDD logic
...
+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
2015-09-25 19:11:23 +03:00
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
85ffc25ec5
ad_tdd_sync: Update the synchronization logic
...
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
5a566b9e5d
ad_tdd_control: Add delay compensation for the control lines
2015-09-09 12:24:26 +03:00
88f806f584
ad9361- alt io matching
2015-08-27 11:55:24 -04:00
74e72021f7
ad9361- ensm through dev-if
2015-08-27 11:41:53 -04:00
Rejeesh Kutty
Istvan Csomortani
AndreiGrozav
Istvan Csomortani
Adrian Costina