Commit Graph

185 Commits (f5ac0f701941147265cf136de56d0589c483f955)

Author SHA1 Message Date
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
Adrian Costina f2d2092297 axi_dacfifo: Add don't touch for the constraints to apply 2019-08-01 18:15:45 +03:00
Arpadi fe09acaa2f up_axi_update: ADDRESS_WIDTH parameter is now a localparam
ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2;
up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
2019-07-26 11:58:58 +03:00
Istvan Csomortani 04ce10a570 cosmetics: Change Altera to Intel in comments 2019-06-29 06:53:51 +03:00
Istvan Csomortani b0fbe1bb57 util_clkdiv: Seperate the IP source into an intel and xilinx version 2019-06-29 06:53:51 +03:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Adrian Costina 81bcf9f6fc util_adxcvr: Cleanup whitespaces for GTY4 instantiations 2019-06-25 15:35:49 +03:00
Istvan Csomortani 20b0c92a1f iodelay: Expose the REFCLK_FREQUENCY parameter 2019-06-11 18:13:06 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
Adrian Costina a0d738e1a9 util_adxcvr: Add GTH parameters for line rate of 15Gbps 2019-05-24 11:05:36 +03:00
Laszlo Nagy f45408d6a9 util_adxcvr: Expose GTY4 parameters required for 15Gbps link
These parameters must be overwritten when the link is at 15Gbps.
The parameters have a GTY4_ prefix since the same parameters are shared
between GTY4 and GTH4 having different default values.
2019-05-09 15:33:15 +03:00
Istvan Csomortani 42d2738a30 axi/util_adxcvr: Add GTYE4 transceiver support 2019-04-12 16:19:54 +03:00
AndreiGrozav 23841478c6 Remove library/scripts/common_bd.tcl
Remove the script from the file list of the IPs that previously used it.
axi_clkgen: Add independent adi_auto_assign_device_spec proc
2019-04-09 16:07:14 +03:00
AndreiGrozav 7dcaaea04e library: Update scripts/adi_ad_ip.tcl and IPs
Fix library makefiles dep list using generic vendor info reg

Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure.
This change will simplify the process of generating makefiles for each library.
Removing the bd.tcl script from the adi_ip_files list will remove it from the
make dependency list.
2019-04-09 16:07:14 +03:00
AndreiGrozav 4ae5a6d3d8 library/IPs: Auto-generate bd.tcl Update
Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to
auto-generate bd.tcl for:

  - axi_ad5766/axi_ad5766_ip.tcl
  - axi_ad6676/axi_ad6676_ip.tcl
  - axi_ad9122/axi_ad9122_ip.tcl
  - axi_ad9144/axi_ad9144_ip.tcl
  - axi_ad9152/axi_ad9152_ip.tcl
  - axi_ad9162/axi_ad9162_ip.tcl
  - axi_ad9250/axi_ad9250_ip.tcl
  - axi_ad9265/axi_ad9265_ip.tcl
  - axi_ad9361/axi_ad9361_ip.tcl
  - axi_ad9371/axi_ad9371_ip.tcl
  - axi_ad9434/axi_ad9434_ip.tcl
  - axi_ad9467/axi_ad9467_ip.tcl
  - axi_ad9625/axi_ad9625_ip.tcl
  - axi_ad9671/axi_ad9671_ip.tcl
  - axi_ad9680/axi_ad9680_ip.tcl
  - axi_ad9684/axi_ad9684_ip.tcl
  - axi_ad9739a/axi_ad9739a_ip.tcl
  - axi_ad9963/axi_ad9963_ip.tcl
  - axi_adrv9009/axi_adrv9009_ip.tcl
  - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
  - axi_hdmi_tx/axi_hdmi_tx_ip.tcl
  - xilinx/axi_adxcvr/Makefile
  - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
  - xilinx/util_adxcvr/Makefile
  - xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-30 11:26:11 +02:00
AndreiGrozav 66823682b6 Add FPGA info parameters flow
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
2019-03-30 11:26:11 +02:00
Istvan Csomortani 04af519af8 axi_adxcvr: Re-indent ports 2019-03-21 14:30:39 +02:00
Istvan Csomortani 845c369c6b axi_adcvr: Add initial value for reg port definition 2019-03-21 14:30:39 +02:00
Istvan Csomortani 8996044978 axi_adxcvr: Fix warning related to up_es_reset
Fix the following warning:

WARNING: [Synth 8-2611] redeclaration of ANSI port up_es_reset is not allowed

Also make sure, that in all configurations, the register has a diver.
2019-03-21 14:30:39 +02:00
Adrian Costina 47f7894881 util_adxcvr: Initial commit for QPLL1 support (GTH3 and GTH4) 2019-02-11 17:20:08 +02:00
Laszlo Nagy 3d7a376f8b Makefile: update makefiles 2018-12-21 17:32:48 +02:00
Adrian Costina a5b7699bd5 axi_adxcvr: Fix typo in initial parameters values 2018-11-16 14:18:33 +02:00
Adrian Costina e1f15f946b axi/util_adxcvr: Add register to control eyescan reset 2018-11-16 14:18:33 +02:00
Adrian Costina b4ea058085 axi_adxcvr: axi_adxcvr_es.v cleanup trailing whitespaces 2018-11-16 14:18:33 +02:00
Adrian Costina 98d3d44fd1 axi_adxcvr: Fix eyescan support for ultrascale plus devices 2018-11-16 14:18:33 +02:00
AndreiGrozav 251ea9471c Remove Xilinx 6 series support
The primitives are not used or supported by the newer versions of Vivado.
2018-10-17 10:06:40 +03:00
Istvan Csomortani 5b5218250b axi_dacfifo: Move util_dacfifo_bypass module to util_dacfifo IP 2018-10-11 16:57:30 +03:00
Istvan Csomortani 42127c07fc util_adxcvr: Expose QPLL and CPLL *_CFG attributes 2018-10-04 14:37:02 +03:00
Istvan Csomortani 740715c6b3 util_adxcvr: Update GHTE4 input port from the wizard 2018-10-04 14:37:02 +03:00
Istvan Csomortani 0d3e05b311 axi|util_adxcvr: Expose TX configurable driver ports
Expose the TX configurable driver ports, more specifically the
TX_DIFFCTRL, TX_POSTCURSORE and TX_PRECURSORE for software. This
provides a soft tunning capability of the transmit side of the
transceivers, in cases where the insertion loss of the channel is too
high or low, comparing to the default value supported by the default
configuration of the GTs.

You can find information about these configuration ports under the
section called 'TX Configurable Driver' in the GT transceivers user
guide. (UG476, UG576)
2018-10-04 14:37:02 +03:00
Istvan Csomortani 8fc6ee8851 util_adxcvr: Define all GTHE4 attribute in binary
This commit does not contain any functional modification.

Because the wizard generates the attributes in binary, we should use
binary mode too, so we can compare different configurations more easily.
2018-10-04 14:37:02 +03:00
Istvan Csomortani e31cfe5639 util_adxcvr_xch: GTHE4 connect CPLL_FBDIV_45 attribute 2018-10-04 14:37:02 +03:00
Istvan Csomortani 99a1768813 Revert "util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate"
This reverts commit 9a74a40c49.
2018-10-04 14:37:02 +03:00
Adrian Costina b01cf35cf7 axi_adcfifo: Fix constraints to apply also to Ultrascale devices
Used IS_SEQUENTIAL instead of PRIMITIVE_SUBGROUP==flop to identify ff related constraints
2018-09-07 17:44:47 +03:00
Istvan Csomortani af5c71a9b2 axi|util_adxcvr: Delete reset interface inference for PLL resets
The Xilinx's reset interface expect that every reset have an associated
interface and clock signal. The tool will try to find its clock and interface,
and automatically associated clock signal to it.

The PLL resets are individual asynchronous resets. To simplify the design
and avoid invalid critical warnings all the reset interface inference
for the PLL resets were removed.
2018-08-23 18:41:48 +03:00
Adrian Costina 9a74a40c49 util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate
Left new parameters values in binary, as that's the way they are generated with the wizard, so future diff should be easier
2018-08-23 18:06:32 +03:00
Istvan Csomortani 5b01df91ac ad_rst: All the synchronization registers have to have ASYNC_REG TRUE 2018-08-14 17:54:14 +03:00
Istvan Csomortani 472b12feb7 ad_rst: Update the reset synchronizer module
For a proper reset synchronization, the asynchronous reset signal should
be connected to the reset pins of the two synchronizer flop, and the
data input of the first flop should be connected to VCC.

In the first stage  we're synchronizing just the reset de-assertion, avoiding
the scenario when different parts of the design are reseting at different time,
causing unwanted behaviours.

In the second stage we're synchronizing the reset assertion.

The module expects an ACTIVE_HIGH input reset signal, and provides an ACTIVE_LOW
(rstn) and an ACTIVE_HIGH (rst) synchronized reset output signal.
2018-08-06 21:24:41 +03:00
Istvan Csomortani c152b60137 ad_mem_asym: Improve the implementation of the asymmetric RAM
Because the read interface got a read enable port too, update all the
ad_mem_asym instances.
2018-08-06 17:29:05 +03:00
AndreiGrozav 568f2e180f ad_mul.v: Add parameters for A and B input widths
The out width will be A + B.
This change is backward compatible and it applies to both Altera and Xilinx.
2018-07-18 18:19:30 +03:00
Istvan Csomortani b3cafb2e39 axi_dacfifo: Always use equal or not equal 2018-06-13 14:58:49 +01:00
Istvan Csomortani a8330402d2 axi_dacfifo: Fix address buffer read logic
The FIFO in the address buffer should work in first-word fall-through mode.
To achieve this the read enable of the memory must be always 1.
2018-06-13 14:58:49 +01:00
Istvan Csomortani aba355b4ce axi_dacfifo: Counters must use 1'b1 for incrementation 2018-06-13 14:58:49 +01:00
Istvan Csomortani a2fc1f25ca axi_dacfifo: Delete unused registers/nets 2018-06-13 14:58:49 +01:00
Istvan Csomortani 97800745db util_dacfifo_bypass: Update comments 2018-06-11 17:26:04 +03:00
Istvan Csomortani 5d3b2b1550 [axi|avl]_dacfifo: Fix the util_dacfifo_module
Fix the read side of the CDC data FIFO. The read address generation did not
function correctly.

Redesign the read side of the FIFO, and make sure that it becomes empty after
the DMA transfer ends; and never get stock in a cyclic mode.
2018-06-11 17:26:04 +03:00
Istvan Csomortani b338b30964 axi_dacfifo: Cosmetic changes in util_dacfifo_bypass 2018-06-11 17:26:04 +03:00
Istvan Csomortani 04ff8bbff4 util_dacfifo: Fix gray coder/decoder
Make the gray coder/decoder's data width parameterizable.
2018-06-11 17:26:04 +03:00
Lars-Peter Clausen 97abb9d6ab axi_dacfifo: Remove unused signals
The dac_last signal is not used anywhere in the module. Remove it and its
synchronization registers.

Fixes the following warnings:
  [Synth 8-6014] Unused sequential element dac_dlast_reg was removed.  ["axi_dacfifo_rd.v":372]
  [Synth 8-6014] Unused sequential element dac_dlast_m1_reg was removed.  ["axi_dacfifo_rd.v":373]
  [Synth 8-6014] Unused sequential element dac_dlast_m2_reg was removed.  ["axi_dacfifo_rd.v":374]

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-11 09:55:07 +02:00
Lars-Peter Clausen 7f18fc5f1c axi_dacfifo: Add missing read-enable signal to ad_mem instance
Commit bfc8ec28c3 ("util_axis_fifo: instantiate block ram in async mode")
added the read-enable (reb) signal to the ad_mem block.

It didn't update the ad_mem instance in axi_dacfifo_address_buffer.v. This
results in the read-enable of the address_buffer being tied to 0.

Fix this by connecting the same signal that increments the read address.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-11 09:55:07 +02:00