0beecea02d
util_adxcvr- ultrascale updates
2016-10-19 13:06:10 -04:00
bf949f1a88
axi_xcvrlb- xcvr updates
2016-10-17 16:16:57 -04:00
1b3fcb5863
util_adxcvr- parameter defaults
2016-10-17 16:10:57 -04:00
cc6ca4f0f2
ad_lvds_in- ultrascale sim device
2016-10-10 10:39:47 -04:00
ff980551e6
ad_serdes: SERDES_FACTOR handover missing
...
In modules ad_serdes_in/ad_serdes_out the handover of the parameter
SERDES_FACTOR did not exist, causing unwanted behavioral in case of
factors less than 8.
SERDES_FACTOR must be hand over to DATA_WIDTH parameter of the SERDES
primitive.
2016-10-10 16:38:42 +03:00
39fdf11ef3
util_adxcvr- rx/tx clocks
2016-10-05 13:53:02 -04:00
7ec93ce8e0
util_adxcvr: Fix some typo
...
GTHE4_CHANNEL is instantiated in case of XCVR_TYPE == 2
2016-10-05 17:42:12 +03:00
4f587d2e48
util_adxcvr: Delete trailing whitespaces
2016-10-05 17:41:40 +03:00
48dd4880a3
util_adxcvr- ultrascale+ initial commit
2016-10-03 16:11:45 -04:00
0e8551545c
util_adxcvr- ultrascale+ initial commit
2016-10-03 16:11:45 -04:00
b4652650e4
util_adxcvr- xcvr_type parameter
2016-10-03 16:11:45 -04:00
63ddcf1e26
util_adxcvr- synthesis warnings fix
2016-10-03 16:11:45 -04:00
6b956066ef
xilinx/ad_lvds*- ultrascale+
2016-09-30 11:55:10 -04:00
9defccef70
dacfifo- axi address map fixes
2016-09-27 14:48:23 -04:00
21b5e9c634
hdlmake- updates
2016-09-21 11:56:03 -04:00
0def596b43
axi_xcvrlb- updates
2016-09-21 11:04:22 -04:00
d497a7b0ae
axi_xcvrlb- constraints
2016-09-21 11:04:22 -04:00
1860d72df6
axi_xcvrlb- updates
2016-09-19 12:39:59 -04:00
5592c2780e
axi_xcvrlb- loopback version
2016-09-19 12:39:59 -04:00
38f1521861
xilinx/ad_serdes_in : Fix some typos
2016-09-19 16:02:52 +03:00
ff0f659a33
xilinx/ad_serdes_clk : Rename parameter MMCM_DEVICE_TYPE to DEVICE_TYPE
2016-09-19 16:02:06 +03:00
6510f92c12
ad_serdes : Cosmetic changes
2016-09-16 14:45:39 +03:00
a2d15acb89
ad_serdes- altera/xilinx sync
2016-09-15 13:33:55 -04:00
3b0c1e02fc
axi_dacfifo: Move IP to library/xilinx
2016-09-15 11:38:16 +03:00
3cbbc771a8
axi_adcfifo: Move IP to library/xilinx
2016-09-15 11:36:47 +03:00
10b9a0e52f
upadated xcvr ips
2016-08-17 15:51:55 -04:00
3427965cd2
adxcvr- add u-gth bufg
2016-08-11 10:00:41 -04:00
829e4155ca
modified transceiver configuration files
2016-08-10 14:59:38 -04:00
1d33d7d7ee
lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common
2016-08-08 15:07:42 +03:00
b806fa3b42
lib_refactoring: Move all the Xilinx common modules to library/xilinx/common
2016-08-08 15:06:10 +03:00
5faf4c4976
cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them
2016-08-05 16:27:52 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
cb23ba8bb7
make- script needs update
2016-08-04 14:17:04 -04:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
2b7c976be5
xcvr- altera/xilinx split
2016-08-04 13:26:10 -04:00
Rejeesh Kutty
Istvan Csomortani
Shrutika Redkar
Adrian Costina