Commit Graph

3353 Commits (f64830364cd46d89df0787cca822854badf0e904)

Author SHA1 Message Date
Sergiu Arpadi f64830364c ad469x: Use axi_pwm_gen; clean-up
Replace axi_pulse_gen with axi_pmw_gen for softare support
considerations. Remove common/config.tcl and update project scripts
accordingly.
2022-11-18 12:54:45 +02:00
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters.
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
Filip Gherman 4e8c816d3f adi_board: Connnect phy_en_char_align only for 8B10B encoding
In ad_xcvrcon procedure from adi_board, phy_en_char_align must be connected only when 8B10B encoding is used,
otherwise this signal does not exists in the JESD ip and will cause an error.

Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-11-01 14:24:31 +02:00
Laszlo Nagy fd0870352b ad9081_fmca_ebz_x_band:zcu102: X band project initial version
HDL project for Stingray: X/Ku Band Phased Array Prototyping System
2022-10-18 09:21:14 +03:00
AndreiGrozav fdb829347a ad9083 based projects: Expose JESD parameters 2022-10-12 17:50:17 +03:00
AndreiGrozav 67a5737fa1 ad9083_vna: Init commit
Compatible with RevB
2022-10-10 17:32:17 +03:00
laurent-19 1eb5f4985b projects/common: Add build files templates carriers. Modified Quartus Versions
The build files are available for the following carriers:
* intel: a10gx, a10soc, c5soc, de10nano, s10soc
* xilinx: coraz7s, kc705, kcu105, vc707, vc709,
	  vck190, vcu118, vcu128, vmk180,
	  zc702, zc706, zcu102, zed

* Added Makefiles, system_constr.sdc, system_qsys intel
* Added Makefiles, system_bd, system_constr xilinx
* de10nano, c5soc: Changed quartus version from 20.1.1 to 21.1.0
  according to last commit update

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-10-05 10:47:21 +03:00
alin724 a4e052e986 cn0506: Update project's directory name in the README file 2022-10-03 10:30:24 +03:00
Liviu.Iacob 5350baffd0 adrv9009zu11eg/common/adrv9009zu11eg_bd: Add logic for TX_JESD_L=4 2022-10-03 10:27:33 +03:00
Liviu.Iacob a95536973f adrv9009/common/adrv9009_bd: Add logic for TX_JESD_L=2 2022-10-03 10:27:33 +03:00
Liviu.Iacob 6a583a8ace projects/fmcomms8: Expose jesd params, add support for TX_JESD_L=4 2022-10-03 10:27:15 +03:00
PopPaul2021 56691bd440 projects/cn0501: Updated with axi_ad7768 IP for Coraz7s 2022-09-30 12:56:57 +03:00
PopPaul2021 9caa15522a
The memory interconnect was moved from HP0 to HP1 on Coraz7s projects (#1023) 2022-09-29 15:14:57 +03:00
Iulia Moldovan 880f37555f ad719x_asdz/coraz7s: Initial commit
* Added interrupt on RDYn on GPIO 32

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2022-09-28 16:30:42 +03:00
Stanca Pop 56290a609d ad4630_fmc: Match project name with folder name 2022-09-26 15:37:49 +03:00
Stanca Pop d2d32458f4 ad9783_ebz: Match project name with folder name 2022-09-26 15:37:49 +03:00
LIacob106 3e297f54dd projects/adrv9009zu11eg: expose jesd params to make and add FMCOMMS8 parameter
Expose JESD parameters to make.
Add FMCOMMS8 parameter.
Changed the name of the observation path to match the rest of the repo.
Replace old dac_data_width formula with a more generic one.
2022-09-26 14:26:31 +03:00
PopPaul2021 8a77d4fb05
coraz7s: Memory interconnect fix (#1014) 2022-09-23 14:58:43 +03:00
Iulia Moldovan 474b8d5bed cn0577/zed: Update xdc to diff_term true. Disable csn in system_top
* Update xdc to use diff_term true instead of diff_term 1
 * Generated xdc using adi_fmc_constr_generator.tcl
 * Make CSN to be inactive
 * Cosmetic changes also

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-09-21 09:42:40 +03:00
laurent-19 6b94259a52 projects/common: Add system_top _project templates
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct code and modify according to guidelines

* Added spacing to ports declaration
* Corrected coding mistakes/misspelling
* Modified/added variables names
* Added seetings (intel) and removed specific optimization settings
* Added assignments to unassigned pins (gpios)

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Correct/Add missing wrapper ports and iobufs

* Added port in wrapper (mainly spi) according to base design file
* Added instances of iobufs where missing
* Corrected gpio assignments or added missing ones
* Corrected minor guidelines mistakes

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

ac701/system_top.v: Change top based on previous projects

 * Looked at fmcomms1, fmcomms2 from hdl_2016_r1 and datasheet

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>

projects/common: Modify templates to build without errors

* Changed path for adi_env.tcl
* Moved adi_project command before assign intel
* Removed unnecessary spi signals
* Added spi ports with default logic
* a10soc: Removed pl-ddr signals and ports
* ac701: system_bd: Modified mdio interface
	 system_project: Added adi_board, adiobuf sourcing
	 system_top: Removed hdmi, i2c, fanpwm, spdif ports
		     according to base design
* c5soc: Added version settings
	 Removed unused gpios
* microzed: system_bd: Enabled RTS1 to use FCLK
	    system_top: Removed hdmi, i2c, unused gpios
* vc709: Separated input from ouput gpio, according to bd
	 Removed unnecessary ports

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>

projects/common: Delete microzed vmk_es templates

* Removed hp0 interconnect from cora base design
* Added extra line to files de10nano

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2022-09-20 17:00:49 +03:00
AndrDragomir 7cde7cd048 projects/scripts: Add fmc constraints generator script
Using the script:
  - make sure that the eval board in use has a common fmc connection file.
  if you created a new one, it should be saved as &project_name_fmc.txt inside
  &project_name/common
  - open a tcl terminal, either inside or outside the project
  - make sure your current directory is &hdl_repo/projects/&project_name/&carrier
  - source the script found at &hdl_repo/project/scripts/fmc_constr_generator.tcl
  - call gen_fmc_constr $parameter_1 $parameter_2:
      - in case of only one fmc port on the carrier call without any parameters
      - if there are two fmc ports on the carrier and you want to use only one,
      the first parameter should contain an indication (fmc_lpc/hpc, fmc0/1, etc.)
      - if there are two fmc ports on the carrier and you want to use both, then
      both parameters should contain an indication
  - the constraints file will be generated in the current directory

Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
2022-09-20 14:11:08 +03:00
AndrDragomir 72378a6d4a projects: Add fmc connection files for eval boards
Creating a new eval board fmc file:
  - docs: Open FMC_eval_board_template.xlsx
  - follow the instructions on the first sheet
2022-09-20 14:11:08 +03:00
AndrDragomir 72cf8f9b5d projects/common: Add fmc connection files for every platform 2022-09-20 14:11:08 +03:00
LIacob106 158c10df34 projects: starndadize the jesd make parameters 2022-09-13 11:53:21 +03:00
Laszlo Nagy d20e604864 ad9082_fmca_ebz/zcu102: Make TPL width overwritable 2022-08-25 12:35:42 +03:00
Laszlo Nagy e332409610 ad9081_fmca_ebz: Make TPL width overwritable 2022-08-25 12:35:42 +03:00
Ionut Podgoreanu 5a06f186ae ad9081_fmca_ebz/common: Use the script to compute the TPL width 2022-08-25 12:35:42 +03:00
AndreiGrozav f955fbc6c0 adi_pd.tcl: Fix sysid branch string
For some newer versions of git where by default color.ui=always.
The colored string captured can result in some special characters
(ASCI escape codes for coloring the terminal output) before and after the string.
e.g:
$ git branch > test.txt
$ vim test.txt
"
* ^[[32mmaster^[[m
  dev_new_device^[[m"

The above escape codes will mess up a terminals color scheme  when this
information is read from sysid and displayed on a terminal.

Use --no-color flag to fix this issue.
2022-08-25 11:36:25 +03:00
Iulia Moldovan 388611866a projects: Fix some Makefiles
* ad9082_fmca_ebz/vcu118
 * dac_fmc_ebz/vcu118

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-25 09:35:55 +03:00
ladace cf4e1b79cf
scripts:adi_env: Change the default version of Quartus Standard to 21.1 (#996)
New version of Quartus Standard for de10nano and sockit  was changed
to 21.1.

Signed-off-by: Liviu Adace <liviu.adace@analog.com>

Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-08-24 17:01:06 +03:00
PopPaul2021 cc18f90579
Added axi_ad7768 IP Core (#989)
* projects/ad7768evb: Initial commit with axi_ad7768 IP

* library/axi_ad7768: Initial commit for AD7768/AD7768-4
2022-08-24 16:57:14 +03:00
ladace 4307e3071f
scripts:adi_env: Change the default version of Quartus Pro to 21.4 (#988)
New version of Quartus Pro for A10SOC, A10GX and S10SOC was changed
to 21.4. Is known that some projects will not build anymore due to
timming violations.
2022-08-18 17:08:29 +03:00
Iulia Moldovan dde37124a4 scripts: Update Vivado version to 2021.2
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
PopPaul2021 0595f93452
AD777x support for ZedBoard and DE10Nano (#937)
* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.

* library/axi_ad777x: Initial commit for Xilinx and Intel

* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
2022-08-10 11:29:05 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Laszlo Nagy d48b1bcdce ad9081_fmca_ebz/vck190: Expose ref clock parameter 2022-08-04 09:52:57 +03:00
Laszlo Nagy 78333b2c90 ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx 2022-08-04 09:52:57 +03:00
Laszlo Nagy 3379dd3bdb ad9082_fmca_ebz/zcu102: Make JESD_MODE overwritable 2022-08-04 09:50:18 +03:00
Liviu.Iacob 54a22d036c adi_pd.tcl: Fix git_clean_string logic 2022-08-02 17:11:49 +03:00
Sergiu Arpadi 94c4a291a7 cn0561_coraz7s: Fix gpio connections 2022-08-02 17:11:19 +03:00
Sergiu Arpadi bb3027995a sysid: Add sysid support for de10nano
make adv7513

make 0540
2022-08-02 14:15:34 +03:00
Laszlo Nagy c748b3bbc7 ad9082_fmca_ebz/zc706: Fix parameters
Match default parameters for L=4 M=8 mode with 10Gbps.
The L=8 M=4 would require lane rate of 15Gbps that is not supported on
zc706.
2022-08-01 16:40:03 +03:00
Laszlo Nagy aae7971689 ad9082_fmca_ebz/vcu118: Fix default lane rate parameter 2022-08-01 16:40:03 +03:00
Laszlo Nagy aed7032e0c ad9082_fmca_ebz/zcu102: Fix default lane rate parameter 2022-08-01 16:40:03 +03:00
Laszlo Nagy 2b274f945f ad9081_fmca_ebz: Reset cpack with Rx data offload 2022-08-01 12:47:26 +03:00
Filip Gherman d48ab915a5 vcu128: Connect sys_mb_rstgen/ext_reset_in accordingly
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-07-29 20:05:08 +03:00
alin724 6aa899f161 scripts/adi_project_xilinx.tcl: Add new constraints file support 2022-07-20 14:36:04 +03:00
alin724 9864d96096 Merge CN0506 projects into a parameterized one 2022-07-20 14:36:04 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Laszlo Nagy 171daab8f2 ad9081_fmca_ebz: a10soc: Update resistor change comment
A board rework is required so the clocks, chip selects or sync signal reach the part correctly.  Without this the link will not come up.
2022-06-21 14:19:58 +03:00