Export the reset signal for the link clock domain. This can be used by
external logic that is in the link clock domain to reset itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Enabling the phase alignment mode of the FPLL seems to break manual
re-calibration, which is required when changing the lane rates. The
calibration seems to select the wrong VCO frequency band and the PLL no
longer locks.
Disable phase alignment mode for now, this has a negative effects on
deterministic latency, but it is better than not working at all.
Waiting for feedback from Altera/Intel on how to make manual re-calibration
work in phase alignment mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
To be able to check the FPLL re-configuration arbitration status from
software enable the avmm_busy flag in the register map.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Add a wrapper module for Altera/Intel platforms that instantiates and
connects all the components required to for a JESD204 link.
The following components are created:
* Transceiver for each lane
* Transceiver lane PLL (TX only)
* Transceiver reset controller
* Link PLL
* JESD204 link layer processing
* JESD204 link layer processing control interface
* axi_adxcvr link management peripheral
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Adrian Costina
Lars-Peter Clausen