pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Adrian Costina	1b1edd1b03	jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps	2017-10-25 14:36:54 +01:00
Lars-Peter Clausen	4df841addc	jesd204: Add soft logic PCS Add soft logic PCS that performs 8b10b encoding for TX and character pattern alignment and 8b10b decoding for RX. The modules are intended to be used in combination with a transceiver that does not have these features implemented in hard logic PCS. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2017-08-21 11:09:42 +02:00

Author

SHA1

Message

Date

Adrian Costina

1b1edd1b03

jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps

2017-10-25 14:36:54 +01:00

Lars-Peter Clausen

4df841addc

jesd204: Add soft logic PCS

Add soft logic PCS that performs 8b10b encoding for TX and character
pattern alignment and 8b10b decoding for RX.

The modules are intended to be used in combination with a transceiver that
does not have these features implemented in hard logic PCS.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

2017-08-21 11:09:42 +02:00

2 Commits (f692d7bc40de1258cad2d1aa7cce9e2143b0cb26)