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3445 Commits (f7190dbbfd94b4c70265c5f5e58025dbb38bdb8f)

Author SHA1 Message Date
Istvan Csomortani f7190dbbfd adxcvr: Update Makefiles 2017-04-03 12:38:40 +03:00
Istvan Csomortani fa5f81f6c6 axi_dacfifo: Fix clock for read address generation 2017-04-03 10:39:17 +03:00
Istvan Csomortani 7cb7bc111e axi_dacfifo: Delete unused wires 2017-04-03 10:38:50 +03:00
Istvan Csomortani 14b4c4cf5f axi_dacfifo: Define constraint for bypass 
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
 2017-04-03 10:38:28 +03:00
Istvan Csomortani 06605ed1e1 axi_dacfifo: Register the dac_valid signals 2017-04-03 10:38:09 +03:00
Istvan Csomortani 77081a6233 axi_dacfifo: Data from DMA is validated with dma_ready too 2017-04-03 10:37:45 +03:00
Istvan Csomortani af3a4f5fc9 axi_dacfifo: axi_dvalid should come from dacfifo_rd module 2017-04-03 10:37:30 +03:00
Istvan Csomortani b30041f7f3 axi_dacfifo: Redesign the bypass functionality 2017-04-03 10:37:08 +03:00
Istvan Csomortani 434d1ea52c axi_dacfifo: Fix constraints 2017-04-03 10:36:46 +03:00
Istvan Csomortani 4bda798f13 Merge branch 'dev' into hdl_2016_r2 
Update the release branch with all the recent fixes.
 2017-02-21 10:56:52 +02:00
Adrian Costina 040b61de60 fmcadc5: Updated default parameters 2017-02-20 17:13:58 +02:00
Rejeesh Kutty a15e05c497 adcfifo- remove axi-byte-width parameter 2017-02-17 15:29:10 -05:00
Rejeesh Kutty cb3d1883bc fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers 2017-02-17 15:21:33 -05:00
Istvan Csomortani 981a61bf16 axi_dacfifo: Clean up the axi_dacfifo_wr.v module 2017-02-17 18:40:02 +02:00
Adrian Costina 3e5054247b scripts: For altera projects, when it doesn't meet timing rename the generated sof 2017-02-17 11:08:50 +02:00
Adrian Costina e8bcbb74da scripts: fixed tcl syntax for altera projects not meeting timing 2017-02-16 21:21:51 +02:00
Istvan Csomortani f10866e4c3 axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter 2017-02-16 19:54:41 +02:00
Istvan Csomortani 95a4ea20c8 axi_dacfifo: Delete redundant parameter BYPASS_EN 2017-02-16 19:53:44 +02:00
Adrian Costina 8453d758c2 scripts: If an altera project doesn't meet timing, rename the sof 2017-02-16 19:20:49 +02:00
Istvan Csomortani 343d0472d4 fmcadc2: Move GT setting to common/system_bd.tcl 2017-02-16 14:56:25 +02:00
Istvan Csomortani 07184b31d2 fmcadc2: Define default clock selection for Xilinx GTs 2017-02-16 12:35:24 +02:00
Adrian Costina 358aa48c76 axi_adc_decimate: Fix assignment width 2017-02-15 11:38:43 +02:00
Adrian Costina 86c279c238 pzsdr1: ccbox, moved I2S core to DMA0 and DMA1 to fix critical warnings 2017-02-14 14:51:49 +02:00
Adrian Costina 46290193f3 pzsdr2: ccusb, renamed clk_out to clkout_in 2017-02-14 11:58:11 +02:00
Adrian Costina 27119343f2 pzsdr2: ccusb, connect unused clock pins to GND 2017-02-14 11:56:54 +02:00
Adrian Costina fa37f4dd0a pzsdr2: Don't set a disabled parameter 2017-02-14 11:56:08 +02:00
Adrian Costina 6a9b7580de pzsdr1: ccusb, renamed clk_out to clkout_in 2017-02-14 11:54:46 +02:00
Adrian Costina acef0113d1 pzsdr1: ccusb, connect unused clock pins to GND 2017-02-14 11:50:37 +02:00
Adrian Costina 46883731eb pzsdr1: Don't set a disabled parameter 2017-02-14 11:50:06 +02:00
Adrian Costina c6ee76421b axi_usb_fx3: Fixed clock domain association 2017-02-14 11:48:07 +02:00
Adrian Costina a569b6bf0c pluto: Interpolation, connect fifo_rd_valid to s_axis_data_tvalid 2017-02-13 18:08:52 +02:00
Adrian Costina 7c86b038ef util_fir_int: manually request data at 1/8 clock frequency 2017-02-13 18:05:59 +02:00
Adrian Costina e215a091b2 m2k: standalone, added explicit fclk_clk0 and fclk_clk1 constraints 2017-02-13 12:02:59 +02:00
Adrian Costina 4e62fb0ef3 m2k: Add reset circuitry on the logic_analyzer clock domain 2017-02-13 12:02:11 +02:00
Istvan Csomortani 5fa6dba333 Make: Update Makefiles 2017-02-10 16:32:58 +02:00
Istvan Csomortani f5f1f47691 ad9467_fmc: Delete asynchronous clock group definition 
This is a very bad way to handle timing. All the false path
should be defined explicitly, rather than define asynchronous clock
domains.
 2017-02-10 16:21:35 +02:00
Istvan Csomortani 0dae754f2d axi_adxcvr: Add rparam register to Altera XCVR 2017-02-10 16:19:17 +02:00
Istvan Csomortani 24daffcf5c spi_engine: Set up default driver value for input ports 2017-02-07 12:30:46 +02:00
Istvan Csomortani 47db0d80fe axi_ad7616: Set up default driver value for input ports 2017-02-07 12:29:21 +02:00
Rejeesh Kutty c39ed08edd zcu102/*- actual clock == desired clock 2017-02-06 12:53:47 -05:00
Rejeesh Kutty 58872aa3ef fmcomms2/zc706pr- prcfg is a single clock synchronous design 2017-02-06 10:59:18 -05:00
AndreiGrozav 971bcbb0fc fmcomms1: Remove project 2017-02-03 16:42:44 +02:00
Rejeesh Kutty 096274a033 daq2/zcu102- fix refclock pin swap 2017-02-03 09:26:07 -05:00
Rejeesh Kutty 7c363cd5a7 daq3/a10gx/system_constr.sdc- fix typo 2017-02-03 09:26:07 -05:00
Rejeesh Kutty 35f660fe06 fmcjesdadc1/vc707- constraint clean-up 2017-02-02 15:05:49 -05:00
Rejeesh Kutty d46352928a fmcomms5- fix ovf net connections 2017-02-02 14:24:06 -05:00
Rejeesh Kutty a57fb5f82f library/ad9122- constraints clean-up 2017-02-02 14:21:41 -05:00
Rejeesh Kutty 1e54b5230f axi_adxcvr- add m_axi associated clock 2017-02-02 11:17:56 -05:00
Adrian Costina 6aadb49e80 m2k: Remove use board flow from the standalone version 2017-02-02 12:58:58 +02:00
Adrian Costina 0d0c3e99fd m2k: Added I2C pull-ul, removed SLEW constraints 2017-02-02 12:35:46 +02:00