3 Commits (f7e3703b98a6ae76b169ff45eecdee08b318a345)

Author	SHA1	Message	Date
Adrian Costina	e40311eee9	adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz	2016-09-29 09:14:37 +01:00
Adrian Costina	2d307d5f58	a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design	2016-09-24 10:06:35 +03:00
Adrian Costina	40c9fc92c1	a10soc: Switched to tcl flow	2016-09-08 11:31:06 +03:00