c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
c3739b1f30
Fix copy-paste typo in *_ip.tcl
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- axi_ad9162
- axi_ad9434
- axi_ad9625
- axi_hdmi_tx
2019-07-29 15:37:30 +03:00
363494ab9c
library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl
2019-06-29 06:53:51 +03:00
7dcaaea04e
library: Update scripts/adi_ad_ip.tcl and IPs
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Fix library makefiles dep list using generic vendor info reg
Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure.
This change will simplify the process of generating makefiles for each library.
Removing the bd.tcl script from the adi_ip_files list will remove it from the
make dependency list.
2019-04-09 16:07:14 +03:00
4ae5a6d3d8
library/IPs: Auto-generate bd.tcl Update
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Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to
auto-generate bd.tcl for:
- axi_ad5766/axi_ad5766_ip.tcl
- axi_ad6676/axi_ad6676_ip.tcl
- axi_ad9122/axi_ad9122_ip.tcl
- axi_ad9144/axi_ad9144_ip.tcl
- axi_ad9152/axi_ad9152_ip.tcl
- axi_ad9162/axi_ad9162_ip.tcl
- axi_ad9250/axi_ad9250_ip.tcl
- axi_ad9265/axi_ad9265_ip.tcl
- axi_ad9361/axi_ad9361_ip.tcl
- axi_ad9371/axi_ad9371_ip.tcl
- axi_ad9434/axi_ad9434_ip.tcl
- axi_ad9467/axi_ad9467_ip.tcl
- axi_ad9625/axi_ad9625_ip.tcl
- axi_ad9671/axi_ad9671_ip.tcl
- axi_ad9680/axi_ad9680_ip.tcl
- axi_ad9684/axi_ad9684_ip.tcl
- axi_ad9739a/axi_ad9739a_ip.tcl
- axi_ad9963/axi_ad9963_ip.tcl
- axi_adrv9009/axi_adrv9009_ip.tcl
- axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
- axi_hdmi_tx/axi_hdmi_tx_ip.tcl
- xilinx/axi_adxcvr/Makefile
- xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
- xilinx/util_adxcvr/Makefile
- xilinx/util_adxcvr/util_adxcvr_ip.tcl
2019-03-30 11:26:11 +02:00
66823682b6
Add FPGA info parameters flow
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Common basic steps:
- Include/create infrastructure:
* Intel:
- require quartus::device package
- set_module_property VALIDATION_CALLBACK info_param_validate
* Xilinx
- add bd.tcl, containing init{} procedure. The init procedure will be
called when the IP will be instantiated into the block design.
- add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
- create GUI files
- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files
axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
2019-03-30 11:26:11 +02:00
74b922f9f8
axi_*: Infer clock and reset signals of an IP
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A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.
The following IPs tcl script was updated:
- axi_ad9434
- axi_hdmi_tx
- util_cpack
- util_adxcvr
- axi_ad6676
- axi_ad9625
- axi_ad9379
- axi_ad9265
- util_tdd_sync
- util_rfifo
- util_wfifo
- axi_ad9361
- axi_ad9467
- util_upack
- axi_dacfifo
- axi_ad9152
- axi_ad9680
- util_clkdiv
- axi_ad9122
- axi_ad9684
- axi_mc_speed
- axi_mc_current_monitor
- axi_mc_controller
- util_gmii_to_rgmii
- util_adxcvr
- axi_ad9379
- axi_hdmi
- library
- axi_fmcadc5_sync
- util_adcfifo
- util_mfifo
- axi_jesd204_rx
- axi_jesd204_tx
- axi_ad9361
- axi_adxcvr_ip
2018-04-11 15:09:54 +03:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
873fbfd6d7
library: Update scripts with new constraints
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Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0
2017-03-30 16:16:02 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
0411ad2386
axi_ad9434: Update constraints
2015-09-23 14:26:55 +03:00
7b858bc5ad
Revert commit 6b99ce
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Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
6b99ce2482
library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2
2015-08-20 18:17:38 +03:00
ad743c8403
axi_ad9434: This IP core does not have 'data underflow' port
2015-06-18 16:51:42 +03:00
8a1f4bf5f6
ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports
2015-06-09 14:21:12 +03:00
91b0f70972
library: remove drp cntrl
2015-06-02 09:58:57 -04:00
ac79c65b81
axi_ad9434: Added CDC and reset constraints
2015-04-23 10:28:46 +03:00
66baf6ac3e
axi_ad9434: Deleted unused ip file
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ad_lvds_in.v is not used in this ip core.
2014-10-07 17:47:08 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
Iulia Moldovan
Iacob_Liviu
AndreiGrozav
Istvan Csomortani
Adrian Costina
Istvan Csomortani
Rejeesh Kutty