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18 Commits (faa5e3d667959809db77900cb0e22c75fd751671)

Author SHA1 Message Date
Istvan Csomortani faa5e3d667 ad_serdes_clk: Fix generate block 2017-04-20 18:49:00 +03:00
Istvan Csomortani f0da125a4e ad_mmcm_drp: Fix generate block 
Can not be multiple 'if' statements inside a generate block. If there are
multiple cases use if/esle statement, but always should be one single
if/else inside a generate.
 2017-04-20 18:43:37 +03:00
Lars-Peter Clausen 09ffe42603 ad_lvds_in: Allow to disable IDELAY 
The IDELAY is not always required, but it eats up power when instantiated. Allow to disable it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:39 +02:00
Lars-Peter Clausen 45f87b46c2 ad_lvds_in: Use "SAME_EDGE" mode 
Currently the IDDRs are configured in SAME_EDGE_PIPELINED mode, but then
the negative data is delayed by an additional clock cycle. This is the same
behaviour as using the IDDR in SAME_EDGE mode.

Switching to SAME_EDGE mode removes extra pipelining registers while
maintaining the same behaviour.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2017-04-18 12:17:39 +02:00
Adrian Costina fc7f2ef11b ad_serdes_out: allow selection between DDR/SDR configuration and output single ended data 2017-04-18 12:17:39 +02:00
Adrian Costina 166a4c53d5 ad_serdes_clk: allow for single ended clock input, made BUFR_DIVIDE configurable 2017-04-18 12:17:39 +02:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Istvan Csomortani 8ba6012b6b restructure: Move xilinx specific constraints to /library/xilinx/common/ 2017-03-30 16:16:02 +03:00
Rejeesh Kutty a2b2ebbed2 ad_lvds_in- ultrascale/ultrascale+ sim device mess 2017-01-21 20:54:21 -05:00
Rejeesh Kutty cc6ca4f0f2 ad_lvds_in- ultrascale sim device 2016-10-10 10:39:47 -04:00
Istvan Csomortani ff980551e6 ad_serdes: SERDES_FACTOR handover missing 
In modules ad_serdes_in/ad_serdes_out the handover of the parameter
SERDES_FACTOR did not exist, causing unwanted behavioral in case of
factors less than 8.
SERDES_FACTOR must be hand over to DATA_WIDTH parameter of the SERDES
primitive.
 2016-10-10 16:38:42 +03:00
Rejeesh Kutty 6b956066ef xilinx/ad_lvds*- ultrascale+ 2016-09-30 11:55:10 -04:00
Istvan Csomortani 38f1521861 xilinx/ad_serdes_in : Fix some typos 2016-09-19 16:02:52 +03:00
Istvan Csomortani ff0f659a33 xilinx/ad_serdes_clk : Rename parameter MMCM_DEVICE_TYPE to DEVICE_TYPE 2016-09-19 16:02:06 +03:00
Istvan Csomortani 6510f92c12 ad_serdes : Cosmetic changes 2016-09-16 14:45:39 +03:00
Rejeesh Kutty a2d15acb89 ad_serdes- altera/xilinx sync 2016-09-15 13:33:55 -04:00
Istvan Csomortani 1d33d7d7ee lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common 2016-08-08 15:07:42 +03:00
Istvan Csomortani b806fa3b42 lib_refactoring: Move all the Xilinx common modules to library/xilinx/common 2016-08-08 15:06:10 +03:00