Istvan Csomortani
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faa5e3d667
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ad_serdes_clk: Fix generate block
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2017-04-20 18:49:00 +03:00 |
Adrian Costina
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166a4c53d5
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ad_serdes_clk: allow for single ended clock input, made BUFR_DIVIDE configurable
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2017-04-18 12:17:39 +02:00 |
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Istvan Csomortani
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ff0f659a33
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xilinx/ad_serdes_clk : Rename parameter MMCM_DEVICE_TYPE to DEVICE_TYPE
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2016-09-19 16:02:06 +03:00 |
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Istvan Csomortani
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6510f92c12
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ad_serdes : Cosmetic changes
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2016-09-16 14:45:39 +03:00 |
Rejeesh Kutty
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a2d15acb89
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ad_serdes- altera/xilinx sync
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2016-09-15 13:33:55 -04:00 |
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Istvan Csomortani
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b806fa3b42
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lib_refactoring: Move all the Xilinx common modules to library/xilinx/common
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2016-08-08 15:06:10 +03:00 |