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54 Commits (faf5f90299252f2d258b9d5171d5575172665305)

Author SHA1 Message Date
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0 
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
 2021-03-08 11:29:33 +02:00
Istvan Csomortani fe90fc7e57 axi_ad9361: add_instance command must have a version attribute 2020-08-11 10:14:18 +03:00
Laszlo Nagy 00166d86b5 axi_ad9361 : add non DPA mode support 
For Intel projects:
In cases where the clock of source synchronous interface is not routed
through a clock capable pin the DPA receive mode can't be used. Instead
the clock will be routed through a clock buffer from an IO to the clock
tree and from there to the IOPLL.
 2020-02-24 11:31:01 +02:00
Laszlo Nagy 0a34f82c20 axi_ad9361/axi_ad9361_hw.tcl: fix Arria 10 fpga selection 2020-02-24 11:31:01 +02:00
Istvan Csomortani 0f7a3b953a scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
Istvan Csomortani 1e074726db intel_serde: Rename alt_serdes to intel_serdes 2019-06-29 06:53:51 +03:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Istvan Csomortani c4c87c7c7a axi_ad9361: Fix the _hw.tcl script 
This will fix an error introduced by 48d2c9d3 "axi_ad9361: Define a MIMO enabled
parameter"
 2019-06-11 12:39:20 +01:00
Istvan Csomortani 48d2c9d36f axi_ad9361: Define a MIMO enabled parameter 
Define a MIMO_ENABLE parameter for the core, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
 2019-06-10 15:16:47 +03:00
AndreiGrozav 66823682b6 Add FPGA info parameters flow 
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
 2019-03-30 11:26:11 +02:00
AndreiGrozav 42abe0cf46 axi_ad9361: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00
AndreiGrozav ca81397410 axi_ad9361: : Update for CORDIC algorithm 
Add the new files to the IP list
Propagate DDS parameters to top file
 2018-07-18 18:19:30 +03:00
Lars-Peter Clausen 324da5f112 Remove unused DMA underflow signal from ADC DMA interface 
The ADC DMA will never underflow and unsurprisingly the adc_dunf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-02 17:21:20 +02:00
Lars-Peter Clausen bd251a5fd5 Remove unused DMA overflow signal from DAC DMA interfaces 
The DAC DMA will never overflow and unsurprisingly the dac_dovf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-02 17:21:20 +02:00
Istvan Csomortani 49293f7a87 axi_ad9361: Fix the last incorrect merge 
The last merge broke a couple of source files of this core. This
commit brings all the core to a functional state.
 2017-10-03 09:15:23 +01:00
Istvan Csomortani 89bd8b44d4 Merge branch 'dev' into hdl_2017_r1 2017-09-26 07:42:19 +01:00
Rejeesh Kutty adcd092ba3 library/ad9361- add pps module 2017-07-31 09:06:50 -04:00
Adrian Costina 289b170dfd axi_ad9361: Fix altera lvds interface, reverting to an older working version 2017-07-28 10:09:17 +01:00
Rejeesh Kutty bc4526cc8a axi_ad9361/altera- add 10 support 2017-07-21 10:33:44 -04:00
Rejeesh Kutty a63e268d6e arradio/c5soc- interface updates 2017-07-20 13:05:07 -04:00
Rejeesh Kutty ff037c0286 altera 16.1 ip changes 2017-05-26 10:48:00 -04:00
Istvan Csomortani 10898d6618 constraints: Split the regmap CDC constraint into separate file 2017-05-25 15:12:16 +03:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Rejeesh Kutty 1e0fed82f7 alt_serdes- a10 ddio fixes 2016-11-01 12:41:25 -04:00
Rejeesh Kutty 9f4c5f8060 arradio/ad9361- updates 2016-10-31 15:34:32 -04:00
Rejeesh Kutty a9d03af771 altera- serdes changes 2016-10-28 14:09:18 -04:00
AndreiGrozav 08cef5a745 axi_ad9361: Add Cyclone V SERDES support 2016-10-25 20:24:17 +03:00
AndreiGrozav 369dad60b0 axi_ad9361: Add Altera SERDES interface support 2016-10-11 17:59:19 +03:00
Adrian Costina 6a8ca8107a common: Added common ad_dcfilter stub for altera. 2016-08-16 17:37:16 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Rejeesh Kutty 7485d27d37 ad9361/altera- device-family variable 2016-06-14 12:28:13 -04:00
Rejeesh Kutty 5d437083cc ad9361/altera- a10+ only 2016-06-14 12:19:54 -04:00
Rejeesh Kutty a262eb7ab3 ad9361- output-rst - associated-rst issue? 2016-05-18 13:24:13 -04:00
Rejeesh Kutty d7f0bd1b76 ad9361- add reset sink 2016-05-18 13:24:13 -04:00
Rejeesh Kutty 68329de738 ad9361- interface updates 2016-05-16 12:19:38 -04:00
Rejeesh Kutty 3871d3ce2b ad9361-c5/a10 - updates 2016-05-09 13:54:08 -04:00
Rejeesh Kutty ef6c99ecab library/axi_ad9361: hw component updates 2016-05-04 13:42:12 -04:00
Rejeesh Kutty 243d3e6e41 ad9361- a10soc sdc files 2016-04-29 10:17:35 -04:00
Rejeesh Kutty f411d29e30 ad9361- a10soc changes 2016-04-29 10:17:35 -04:00
Adrian Costina 275ec3d3a8 axi_ad9361: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:21:08 +02:00
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters 
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
 2015-08-19 14:11:47 +03:00
Istvan Csomortani b84afcdcd1 Merge branch 'master' into dev 
Conflicts:
	library/Makefile
	library/axi_ad6676/axi_ad6676_ip.tcl
	library/axi_ad9122/axi_ad9122_core.v
	library/axi_ad9122/axi_ad9122_ip.tcl
	library/axi_ad9144/axi_ad9144_ip.tcl
	library/axi_ad9152/axi_ad9152_ip.tcl
	library/axi_ad9234/axi_ad9234_ip.tcl
	library/axi_ad9250/axi_ad9250_hw.tcl
	library/axi_ad9250/axi_ad9250_ip.tcl
	library/axi_ad9361/axi_ad9361.v
	library/axi_ad9361/axi_ad9361_dev_if_alt.v
	library/axi_ad9361/axi_ad9361_ip.tcl
	library/axi_ad9361/axi_ad9361_rx_channel.v
	library/axi_ad9361/axi_ad9361_tdd.v
	library/axi_ad9361/axi_ad9361_tx_channel.v
	library/axi_ad9625/axi_ad9625_ip.tcl
	library/axi_ad9643/axi_ad9643_channel.v
	library/axi_ad9643/axi_ad9643_ip.tcl
	library/axi_ad9652/axi_ad9652_channel.v
	library/axi_ad9652/axi_ad9652_ip.tcl
	library/axi_ad9671/axi_ad9671_constr.xdc
	library/axi_ad9671/axi_ad9671_ip.tcl
	library/axi_ad9680/axi_ad9680_ip.tcl
	library/axi_ad9739a/axi_ad9739a_ip.tcl
	library/axi_dmac/axi_dmac_constr.sdc
	library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
	library/axi_jesd_gt/axi_jesd_gt_constr.xdc
	library/axi_jesd_gt/axi_jesd_gt_ip.tcl
	library/axi_mc_speed/axi_mc_speed_constr.xdc
	library/common/ad_gt_channel_1.v
	library/common/ad_gt_common_1.v
	library/common/ad_gt_es.v
	library/common/ad_iqcor.v
	library/common/ad_jesd_align.v
	library/common/ad_rst.v
	library/common/altera/ad_xcvr_rx_rst.v
	library/common/up_adc_common.v
	library/common/up_axis_dma_rx.v
	library/common/up_axis_dma_tx.v
	library/common/up_clkgen.v
	library/common/up_clock_mon.v
	library/common/up_dac_common.v
	library/common/up_gt.v
	library/common/up_hdmi_tx.v
	library/common/up_tdd_cntrl.v
	library/common/up_xfer_cntrl.v
	library/common/up_xfer_status.v
	library/util_cpack/util_cpack.v
	library/util_cpack/util_cpack_ip.tcl
	library/util_dac_unpack/util_dac_unpack_hw.tcl
	library/util_jesd_align/util_jesd_align.v
	library/util_jesd_xmit/util_jesd_xmit.v
	library/util_upack/util_upack_ip.tcl
	library/util_wfifo/util_wfifo.v
	library/util_wfifo/util_wfifo_constr.xdc
	library/util_wfifo/util_wfifo_ip.tcl
	projects/arradio/c5soc/system_bd.qsys
	projects/common/vc707/vc707_system_bd.tcl
	projects/common/zc706/zc706_system_plddr3.tcl
	projects/daq2/a10gx/Makefile
	projects/daq2/a10gx/system_bd.qsys
	projects/daq3/common/daq3_bd.tcl
	projects/daq3/zc706/system_bd.tcl
	projects/fmcjesdadc1/a5gt/Makefile
	projects/fmcjesdadc1/a5gt/system_bd.qsys
	projects/fmcjesdadc1/a5gt/system_constr.sdc
	projects/fmcjesdadc1/a5gt/system_top.v
	projects/fmcjesdadc1/a5soc/system_bd.qsys
	projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
	projects/fmcomms1/ac701/system_bd.tcl
	projects/fmcomms1/common/fmcomms1_bd.tcl
	projects/fmcomms1/kc705/system_bd.tcl
	projects/fmcomms1/vc707/system_bd.tcl
	projects/fmcomms1/zc702/system_bd.tcl
	projects/fmcomms1/zc702/system_top.v
	projects/fmcomms1/zc706/system_bd.tcl
	projects/fmcomms1/zc706/system_top.v
	projects/fmcomms1/zed/system_bd.tcl
	projects/fmcomms1/zed/system_top.v
	projects/fmcomms2/ac701/system_constr.xdc
	projects/fmcomms2/common/fmcomms2_bd.tcl
	projects/fmcomms2/kc705/system_constr.xdc
	projects/fmcomms2/kc705/system_top.v
	projects/fmcomms2/mitx045/system_top.v
	projects/fmcomms2/rfsom/system_constr.xdc
	projects/fmcomms2/rfsom/system_top.v
	projects/fmcomms2/vc707/system_top.v
	projects/fmcomms2/zc706/system_bd.tcl
	projects/fmcomms2/zc706/system_constr.xdc
	projects/fmcomms2/zc706/system_top.v
	projects/fmcomms2/zed/system_top.v
	projects/imageon/zc706/system_constr.xdc
	projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
	projects/motcon2_fmc/zed/system_constr.xdc
	projects/motcon2_fmc/zed/system_top.v
	projects/usdrx1/a5gt/Makefile
	projects/usdrx1/a5gt/system_bd.qsys
	projects/usdrx1/common/usdrx1_bd.tcl

Conflicts were resolved using 'Mine' (/dev).
 2015-08-17 15:15:58 +03:00
Adrian Costina 623c3dc333 axi_ad9361: Updated altera core by including tdd related files. Removed deleted ports 2015-07-24 16:41:41 +03:00
Rejeesh Kutty 3101045109 qsys- library group 2015-07-17 10:07:15 -04:00
Rejeesh Kutty e02273781f ad_rst- non lpm version 2015-06-04 10:53:12 -04:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Lars-Peter Clausen 3162540b03 axi_ad9361: Remove the Altera toplevel wrapper 
By setting the AXI controler interface type from axi4 to axi4lite we can use
the normal toplevel file with only a simple modification to add the awprot
and arprot signals.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-11 12:29:13 +02:00
Rejeesh Kutty 6346017763 c5soc: changed to alt_lvds - 250M is too high for cyclone v 2014-07-24 20:51:40 -04:00
Rejeesh Kutty c0e31aa6c2 daq2: latest hardware 2014-07-21 09:06:57 -04:00