This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
The second ADC was removed from the project, as the EV-AD7768-1FMCZ evaluation
board contains only one ADC. Therefore, all the IPs related to the
second ADC have been removed, too.
The data width supported by the spi IPs has been changed from 8 bits to
32 bits, therefore the axis_upscaler(util_axis_upscale_v1_0) and the
m_axis_samples_24(AXI4-Stream Data Width Converter) are no more necessary,
so they have been removed from the design.
The 24 bits width data transfer between the s_axis of axi_ad77681_dma
(AXI DMA Controller) and the offload_sdi of the spi_engine_offload is now made
directly.
In the latest system_top file we are not bringing out all the interrupt
signals from the block design. Delete all interrupt ports from the
system_wrapper instance.
Following projects were changed:
- AD5766_SDZ
- AD7134_FMC
- AD7616_SDZ
- AD77681EVB
- AD7768EVB
- ADAQ7980
Removes a lot of boilerplate code.
Using the new scheme it is possible to add new projects or sub-projects
without having to re-generate any existing Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.
It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Loop back the unused GPIO pins, and add all the SPI interface to system
wrapper instance.
The following system_top modules were changed:
- ad738x_fmc
- ad7616_sdz
- ad77681evb
- ad77681evb
- ad7768evb
- ad9739a_fmc
- ad9434
- adrv9739
- fmcadc5
- ad6676evb
- ad9265
- ad5766
- fmcomms5
- m2k
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
sergiu arpadi
Robin Getz
Adrian Costina
Istvan Csomortani
Stanca Pop
StancaPop
Lars-Peter Clausen
Rejeesh Kutty