68461110aa
Replace link in license header from master to main
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2024-01-16 16:48:45 +02:00
c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
28c06d505f
Add/edit copyright and license for .v, .sv files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
10a87f34d3
projects/fmcomms8: Interconnect m_axi port for rx_xcvr
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Signed-off-by: LIacob106 <liviu.iacob@analog.com>
2023-01-26 15:35:12 +02:00
19249b51db
projects/fmcomms8: JESD support for 2, 4 TX_L and RX/ORX_L
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On zcu102 carrier.
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
2023-01-10 13:06:23 +02:00
6a583a8ace
projects/fmcomms8: Expose jesd params, add support for TX_JESD_L=4
2022-10-03 10:27:15 +03:00
72378a6d4a
projects: Add fmc connection files for eval boards
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Creating a new eval board fmc file:
- docs: Open FMC_eval_board_template.xlsx
- follow the instructions on the first sheet
2022-09-20 14:11:08 +03:00
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
6d504d14cf
fmcomms8: zcu102: Fix lane swapping
2021-02-05 15:07:09 +02:00
dee108ba22
fmcomms8/intel: Fix fPLL configuration
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When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.
The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.
Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
0644edb389
fmcomms8: a10soc: Move RX and Observation to second SDRAM interface
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This is an attempt to get full bandwidth without a FIFO
2020-10-26 18:12:14 +02:00
6621fbec61
fmcomms8: a10soc: Initial commit
2020-10-26 18:12:14 +02:00
4d2e05d5dd
fmcomms8: common: In the SPI module, use ad_iobuf instead of a Xilinx primitive
2020-09-25 11:54:12 +03:00
50d904934a
fmcomms8: Changed the interrupt addresses to be similar with adrv9009zu11eg project
2020-03-06 16:07:02 +02:00
e51d9372cd
fmcomms8: ZCU102: Added DAC FIFO
2020-02-10 11:23:52 +02:00
016a1d540d
fmcomms8: ZCU102: Initial commit
2020-02-10 11:23:52 +02:00
Iulia Moldovan
LIacob106
AndrDragomir
Adrian Costina
Istvan Csomortani