* ad_data_in: Add new logic and explanations
* Added parameters IDELAY_TYPE, DELAY_FORMAT, US_DELAY_TYPE to be used
with the IDELAY instances
* Added explanations
* Added option to bypass IDELAY if it's not instantiated, regardless of
the FPGA_TECHNOLOGY parameter
* Determined a part of the logic for EN_VTC (by the UG) but not for all
modes since we don't have use cases for them
* Changed logic when adding ODELAY: now you must set IODELAY_ENABLE = 1
and FPGA_TECHNOLOGY != NONE if you want it
* ad_data_out:
* Updated ODDR parameter
* Fixed issue with ODDR inputs D1, D2: D1 must be with _p and D2 with _n,
according to the Xilinx template
* Removed _ES1 from IODELAY_SIM_DEVICE
* Added ODELAY for UltraScale
* Before, there was no support for UltraScale/+, and the output data
was completely disconnected from the ODDR
* The support for this was requested in this issue, although as of now we don't
have a design that uses it: https://github.com/analogdevicesinc/hdl/issues/917
* Added parameters ODELAY_TYPE, DELAY_FORMAT, US_DELAY_TYPE to be used
with the ODELAY instances
* Added explanations
* Added option to bypass ODELAY if it's not instantiated, regardless of
the FPGA_TECHNOLOGY parameter
* Determined a part of the logic for the EN_VTC (by the UG) but not for
all modes since we don't have use cases for them
* Changed logic when adding ODELAY: now you must set IODELAY_ENABLE = 1
and FPGA_TECHNOLOGY != NONE if you want it
---------
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.
Projects which use spi_engine.tcl will be updated to account for
these changes.
- Quartus version was updated
- the start_n output port was deteled from system_top.v
- the ""mixed_port_feed_through_mode" parameter of RAM can not have value "old"" warning was disabled
- update Makefile copyright year
Signed-off-by: Paul Pop <paul.pop@analog.com>
bug:
say "make LVDS_CMOS_N=0"
- will set ad_project_dir as LVDSCMOSN0
- will then set system_qip_file as LVDSCMOSN0/system_bd/synthesis/system_bd.qip
- build error reveals system_bd can't be found
- maybe due to setting ad_project_dir as a relative file path
fix:
- set ad_project_dir as an absolute file path
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
If the sampling clock is lower than dclk*number_of_active_lines*32 the interface should wait for the next adc_ready signal to reset the counter.
The adc_valid_p signal should be set high just for a clock period after the sample was captured.
- Issue introduced by commit 173f4a83d4
- When IODELAY_ENABLE was inserted in axi_adrv9001_if for adrv9001_rx (Xilinx instance),
for Intel instance (intel/adrv9001_rx.v) was omitted and caused a build error for
adrv9001/a10soc
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Replaced the existing axi_tdd with the new version
* Added DEFAULT_POLARITY synth parameter and RO register
* Added TDD_STATUS register
* Added TDD_SYNC_RST feature
* Used the asy_ prefix for signals which are not synced
* Added logic to force the state from ARMED to RUNNING when startup_delay=0
* Added feature to finish the burst when the module is disabled before its completion
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
ladace
imoldovan
sergiu arpadi
alin724
AndreiGrozav
laurent-19
Stanca Pop
Paul Pop
Jem Geronimo
Iulia Moldovan
Istvan-Zsolt Szekely
AndrDragomir
LIacob106
Filip Gherman
Ionut Podgoreanu