c6998dd396
scripts- altera conduit
2016-09-12 14:57:50 -04:00
73ebf1225c
axi_adxcvr- ip/phy split
2016-09-12 14:57:50 -04:00
21545ee83f
avl_adxcvr- ip/phy split
2016-09-12 14:57:50 -04:00
8718b7f477
avl_adxphy- ip/phy split
2016-09-12 14:57:50 -04:00
d30ffdb7e9
avl_adxcfg- ip/phy split
2016-09-12 14:57:50 -04:00
9159e31244
axi_adxcvr- compile fixes
2016-09-12 14:57:50 -04:00
5a309d8863
avl_adxphy- split
2016-09-12 14:57:50 -04:00
2a34f9baa8
alt-serdes, in & out
2016-09-12 11:45:23 -04:00
9e0c39a71b
alt_serdes_clk- changes
2016-09-12 10:30:28 -04:00
f4be0524b4
altera/common: Add SERDES related modules
2016-09-09 18:04:41 +03:00
a183e51a12
axi_ad9361: Add parameter R1_MODE_EN
...
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
2016-09-09 16:34:11 +03:00
e42206e510
axi_ad9361: Add a TDD enable/disable parameter
2016-09-09 14:38:28 +03:00
be41a8bcaa
axi_ad9361: Delete debug ports of the tdd module
2016-09-09 14:38:28 +03:00
bbcf2a3ec3
axi_ad9434/axi_ad9434_constr: Change constraint file to resolve critical warning
2016-09-01 17:16:59 +03:00
4ae084ee32
avl_adxcvr- compile fixes
2016-09-01 10:06:28 -04:00
5544e3cf10
axi_adxcvr- compile fixes
2016-09-01 10:06:28 -04:00
230f1526c0
avl_adxcfg- compile fixes
2016-09-01 10:06:28 -04:00
b7ea2efa87
altera- xcvr cores
2016-08-29 15:18:48 -04:00
9799599eee
library/ad9361- add dac clk sel
2016-08-26 10:31:00 -04:00
74bc498a6d
library/common- added dac clock select
2016-08-26 10:31:00 -04:00
10b9a0e52f
upadated xcvr ips
2016-08-17 15:51:55 -04:00
6a8ca8107a
common: Added common ad_dcfilter stub for altera.
2016-08-16 17:37:16 +03:00
e754f0a46a
up_axi- writes dropped by delayed w-responses
2016-08-14 11:21:19 -04:00
3427965cd2
adxcvr- add u-gth bufg
2016-08-11 10:00:41 -04:00
bb9cb86f34
adc/dac- fifo constraints
2016-08-11 10:00:41 -04:00
829e4155ca
modified transceiver configuration files
2016-08-10 14:59:38 -04:00
b8f4e1c0aa
updated 9680 hdl files(to resolve a critical warning)
2016-08-10 14:50:31 -04:00
ccf1c56b33
util_upack: Patch up the description of Altera IP
2016-08-08 16:39:56 +03:00
e9ac4a5a0e
util_rfifo: Patch up the description of Altera IP
2016-08-08 16:39:25 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
aad8c265bc
lib_refactoring: Fix path for CMOS sources
2016-08-08 15:07:54 +03:00
1d33d7d7ee
lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common
2016-08-08 15:07:42 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
90ac7b7ac9
lib_refactoring: Move all Altera module to library/altera/common
...
Move all Altera modules to library/altera/common, delete the
deprecated wrapper files
2016-08-08 15:07:01 +03:00
cb9af99c5d
lib_refactoring: Add ad_mul.v for Altera
2016-08-08 15:06:48 +03:00
b806fa3b42
lib_refactoring: Move all the Xilinx common modules to library/xilinx/common
2016-08-08 15:06:10 +03:00
5faf4c4976
cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them
2016-08-05 16:27:52 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
cb23ba8bb7
make- script needs update
2016-08-04 14:17:04 -04:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
2b7c976be5
xcvr- altera/xilinx split
2016-08-04 13:26:10 -04:00
cba53774ca
axi_dmac: Don't add CDC constraints when all clocks are synchronous
...
When all clocks are synchronous there are no synchronizers and the
constraint for the CDC registers can't find any cells which generates a
warning. To avoid this don't add CDC constraints when all the clocks are
synchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-02 19:30:24 +02:00
aece3f5555
axi_ad9680: Update IP core
...
- added signals so that AD9680 can be connected to altera's xcvr core through an avalon streaming sink
- added DEVICE_TYPE parameter in _hw.tcl, set to 1 for altera
2016-08-01 15:05:30 +03:00
a0ae791395
hdl-vivado-2016.2: Update axi_jesd_gt
...
Infer AXI bus interfaces separately.
2016-08-01 13:53:18 +03:00
fbe3d75eb0
cosmetics: Delete trailing whitespace characters
2016-08-01 13:46:46 +03:00
b99117e686
up_axi: Same cycle BVALID/READY fails on Altera
...
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.
Similar to:
2817ccdb22
2016-08-01 12:17:10 +03:00
58b220ba81
ad_tdd_control: Add an on/off switch to the receive datapath
...
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
2016-08-01 11:49:27 +03:00
7988d2c7a2
adi_ip: remove duplicated errored auto address maps & interfaces
2016-07-29 12:32:19 -04:00
4aa506de8d
adxcvr- added a space?
2016-07-29 09:38:08 -04:00
71dad14e0e
axi_adcfifo- disable auto infer mess-up
2016-07-29 09:37:17 -04:00
39ff059ef6
hdl-vivado-2016.2- productivity decimated again!
2016-07-28 13:44:57 -04:00
d5d61ff518
hdl-vivado-2016.2- productivity decimated again!
2016-07-28 13:44:57 -04:00
52b544bb66
hdl-vivado-2016.2- auto infer bus interfaces
2016-07-28 13:44:57 -04:00
3384d384d3
hdl-vivado-2016.2- infer bus interfaces separately
2016-07-28 13:44:57 -04:00
c316f0dfea
ad9144- synthesis warnings fix
2016-07-28 13:44:57 -04:00
8a2734b43e
up_dac_common- typo- unf register reset
2016-07-28 13:44:57 -04:00
6ebb32a194
library axi-slave missing protection signal added
2016-07-22 12:54:27 -04:00
39a5534e00
hdlmake- updates
2016-07-21 16:10:38 -04:00
5c91e41da8
ad9680- sof + sample delineation
2016-07-21 16:09:33 -04:00
db6d5f509f
library/common- xcvr interface logic
2016-07-21 16:09:33 -04:00
75864f0ce5
util_adxcvr- add constraints file
2016-07-21 16:09:33 -04:00
1435c5f7f7
util_adxcvr- add clock buffers, rst-done, rate on usrclk
2016-07-21 16:09:33 -04:00
8e04e70791
axi_adxcvr- status output for jesd ip
2016-07-21 16:09:33 -04:00
1f25d7f637
axi_adxcvr- self-disable based on num of lanes
2016-07-21 16:09:33 -04:00
c797a579f1
util_adxcvr- rstdone on usrclk2
2016-07-21 16:09:33 -04:00
ced36f6159
up-dac- support iq mode
2016-07-21 11:58:03 -04:00
3a1ecb7463
ad9162- support iq mode
2016-07-21 11:58:03 -04:00
040f72d172
ad_mul_u16: Delete unused module
2016-07-20 14:17:04 +03:00
2dd6bb0cb8
up_drp_cntrl: Delete unused module
2016-07-20 14:17:04 +03:00
af9915b060
up_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
df43ca9332
ad_axis_dma_*: Delete unused modules
2016-07-20 14:17:04 +03:00
46b00aea2d
util_adc_pack: Delete unused IP core
2016-07-20 14:17:04 +03:00
8902a31ca6
util_dac_unpack: Delete unused IP core
2016-07-20 14:17:04 +03:00
634924246a
axi_jesd_xcvr: Delete Makefile
...
This core is an Altera core only, no need for Makefile.
2016-07-20 14:17:04 +03:00
74c220d79e
make: Update Make files
2016-07-20 14:17:04 +03:00
b9a5bb3549
axi_dacfifo: Optimize the AXI read logic
...
Save the valid AXI beats number of the last AXI transaction, and the valid
DMA beats number of the last AXI beat, so the read back logic can use this
data and prevent to feel up the CDC memory with invalid samples. Also in
this way the end of the read back cycle get a more robust control: no more
duplicated samples at the end of the buffer.
2016-07-20 11:49:06 +03:00
e46990e508
axi_dacfifo: Cosmetic changes
...
Rename a few registers and fix indentation.
2016-07-20 11:49:06 +03:00
b48401175a
axi_dacfifo: Optimize the AXI write logic
2016-07-20 11:49:06 +03:00
74f45cff24
axi-ad9625: fix clock ratio to match sampling clock
2016-07-19 16:21:13 -04:00
1df942b752
rfifo- buffer 1 seg before read
2016-07-12 10:24:22 -04:00
4f0d7bd6eb
util_wfifo: read after write is complete
2016-07-11 09:59:31 -04:00
832efdc99c
hdlmake updates
2016-07-08 13:58:56 -04:00
7a03d44e4e
adxcvr- clock buffers are removed
2016-07-08 13:57:27 -04:00
20ac95b1ec
adxcvr- initial commit
2016-07-08 13:57:27 -04:00
48762519b5
make updates
2016-07-06 15:02:00 -04:00
427cc84bb2
axi_ad7616: Rename the physical interface signals to rx_*
...
No functional modification.
2016-07-01 14:45:23 +03:00
d931b2ee64
ad9162 core verilog files
2016-06-30 10:24:01 -04:00
8d558b2538
make: Update Make files
2016-06-29 14:50:07 +03:00
18e28b01fd
axi_ad7616: Add burst counter to the parallel interface
...
With this counter the parallel logic supports the burst sequencer.
2016-06-29 14:17:28 +03:00
e6494b9a74
axi_ad7616: Change the DMA interface type to Write FIFO
2016-06-29 14:11:02 +03:00
64633e519c
Merge remote-tracking branch 'origin/dev_ad7616' into dev
2016-06-29 12:32:39 +03:00
cdf01a492e
library/axi_dacfifo: Update the bypass logic
...
The bypass logic is located between the AXI read controller and the
DAC CDC fifo. When the bypass is enabled the DMAC destination interface
must be clocked with the PL_DDR controller's ui_clk. This way it can easily
switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 12:24:54 +03:00
def47dd536
interfaces: added xcvr interfaces
2016-06-17 12:00:15 -04:00
36fbf4fc42
util_adxcvr: shared xcvr cores
2016-06-17 11:59:42 -04:00
87cf13b0ef
util_adxcvr- system verilog interfaces
2016-06-16 16:41:43 -04:00
80ce7aeb66
util_adxcvr- updates
2016-06-16 16:40:57 -04:00
7c762f63a8
library/axi_dacfifo: Fix the control logic of the write side
...
Fix the control logic for the AXI write transactions.
2016-06-15 13:49:00 +03:00
d5ce137c55
library/axi_dacfifo: Fix reset for a few registers
2016-06-15 13:49:00 +03:00
10090a296e
library/axi_dacfifo: Cosmetic changes
...
Rename a few registers and improve consistency.
2016-06-15 13:49:00 +03:00
7485d27d37
ad9361/altera- device-family variable
2016-06-14 12:28:13 -04:00
5d437083cc
ad9361/altera- a10+ only
2016-06-14 12:19:54 -04:00
dc45287b14
util_adxcvr- added
2016-06-14 12:19:18 -04:00
c19ed4c8ef
axi_hdmi_tx_core: Fixed embedded sync synchronization signals
2016-06-14 14:30:28 +03:00
aee38e1cc9
up_hdmi_tx: Fixed data path width
2016-06-14 14:27:03 +03:00
27fd5f5bdc
modified prbs7 and prbs15 gereration code
2016-06-13 14:44:03 -04:00
83dd7e91c4
deleted pn23 and pn 31, data width yet to be modified
2016-06-13 14:44:03 -04:00
341b7badee
library/scripts: Remove all autogenerated interface in adi_ip_properties_lite
...
There are a few IP, which is configured by using just the adi_ip_properties_lite
process, therefor the remove_all_bus_interface will be called in the end of that
process, to make sure that all the autogenerated interfaces are deleted during the
IP properties setup.
2016-06-10 15:08:05 +03:00
9d1ae436b1
common/util_pulse_gen: Rename the ad_tdd_sync module
2016-06-09 10:07:47 +03:00
abe837e608
util_rfifo: Set an offset for the write addres
2016-06-02 17:34:29 +03:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
3832f2669e
axi_jesd_xcvr: support tx/rx disable
2016-06-01 13:48:51 -04:00
54f398cc36
ad9371-hw- add dsp slice
2016-06-01 13:48:51 -04:00
e1495b89f9
axi_dacfifo: Cosmetic changes
2016-05-27 14:13:55 +03:00
c724c027c4
axi_dacfifo: Fix the synchronizers
2016-05-27 14:13:55 +03:00
183c67aca0
axi_dacfifo: Update the axi write controller
...
Do some refactoring and add a DMA beat counter.
2016-05-27 14:13:55 +03:00
8caa783f5c
axi_dacfifo: Update the constraints
2016-05-27 14:13:55 +03:00
3b6a36e3e2
axi_dacfifo: Increase the ASYM_MEM depth in the DAC side
...
Increase the asymetric memory depth on the DAC side. Increase the
data width of the grey coder and decoder.
The controller fills up the CDC memory with three AXI burst, to prevent
underflow on the wrap arounds.
2016-05-27 14:13:55 +03:00
c8d4f956e7
axi_dacfifo: Update the read back logic
...
Update the readback logic of the FIFO. The controller uses a
relative address counter, which counts the DMA beats. The readback
logic uses the last value of that counter to define the wrapping
address. The aditional data from the last AXI burst, if there is any,
will be dropped.
2016-05-27 14:13:55 +03:00
88e0cfec42
axi_dacfifo: The AXI read and write have the same properties
...
AXI read and AXI write channel have the same SIZE and LENGTH.
2016-05-27 14:13:55 +03:00
aca3038919
axi_dacfifo: No overflow for DAC
2016-05-27 14:13:55 +03:00
81ade7f26c
axi_dacfifo: Fix resets
...
DMA side: axi_resetn is used to reset the address counters
DAC side: GT tx_rst is used to reset the last_address register
2016-05-27 14:13:55 +03:00
578376c8fe
axi_dacfifo: Add bypass logic
2016-05-27 14:13:55 +03:00
f10c1e6e93
axi_hdmi_tx: Remove hdmi_full_range register
2016-05-27 14:04:40 +03:00
05ac271aff
daq3/a10gx- qsys modifications
2016-05-24 03:15:24 -04:00
d254fa841b
library- altera updates
2016-05-23 10:55:07 -04:00
3f00614bc7
axi_jesd_xcvr: rx/tx only select
2016-05-20 16:13:36 -04:00
f1a603a3b1
ad9371- altera ip
2016-05-20 15:16:36 -04:00
09520709b0
make updates
2016-05-20 12:35:45 -04:00
b5b05bb9d1
axi_ad9371: added
2016-05-20 11:41:54 -04:00
bf0b90229a
rfifo/wfifo- qsys ip
2016-05-18 13:24:13 -04:00
7fdaee186c
upack/cpack- qsys ip
2016-05-18 13:24:13 -04:00
a262eb7ab3
ad9361- output-rst - associated-rst issue?
2016-05-18 13:24:13 -04:00
e15893444c
upack- fix interface names
2016-05-18 13:24:13 -04:00
285cbc7225
xfifo- fix sdc/xdc names
2016-05-18 13:24:13 -04:00
d7f0bd1b76
ad9361- add reset sink
2016-05-18 13:24:13 -04:00
bb4ed42a93
ad9361- add missing wires
2016-05-18 13:24:13 -04:00
42b0fabd40
axi_hdmi_tx_core: Fixed data path
2016-05-17 14:41:18 +03:00
68329de738
ad9361- interface updates
2016-05-16 12:19:38 -04:00
421c0519f4
util_rfifo- updates
2016-05-16 12:19:38 -04:00
e05204a86d
util_cpack: interface updates
2016-05-16 12:19:38 -04:00
6bc05fc844
ad_*_in: register post-iob
2016-05-16 12:19:38 -04:00
cd7c9c99ed
ad_*_clk: altera-pll not supported by qsys flow
2016-05-16 12:19:38 -04:00
4fbff45e27
util_wfifo- updates
2016-05-16 12:19:38 -04:00
f515885fc4
util_wfifo: altera ip
2016-05-16 12:19:38 -04:00
58a2a3259c
util_rfifo: updates
2016-05-16 12:19:38 -04:00
82d43783f1
util_rfifo: altera ip
2016-05-16 12:19:38 -04:00
31671bf9d5
util_rfifo: constraints
2016-05-16 12:19:38 -04:00
aadb220a3f
zcu102- updates
2016-05-10 15:40:41 -04:00
3871d3ce2b
ad9361-c5/a10 - updates
2016-05-09 13:54:08 -04:00
9cd6e2da51
quartus-mess- altddio direct instantiation
2016-05-09 13:54:08 -04:00
726ddb6e93
ad_lvds_clk: Fixed assignment mismatched
2016-05-09 10:32:18 +03:00
b0538a03a2
Make: Update
2016-05-06 16:44:24 +03:00
b36c722ec9
up_hdmi_tx: Discard the standard default values
...
Restore the base functionality of the core. Changing the data format
will not set by default its standard maximum and minimum data clipping
ranges.
2016-05-05 13:41:46 +03:00
68d83def01
axi_hdmi_tx_core: Fixed data path
2016-05-05 13:32:25 +03:00
0d2dc2c62b
axi_hdmi_tx: Fixed data bus width
2016-05-05 13:26:59 +03:00
bdfa383622
library/axi_ad9361: tdd false paths
2016-05-04 13:42:12 -04:00
ef6c99ecab
library/axi_ad9361: hw component updates
2016-05-04 13:42:12 -04:00
3b5e44e37d
library/axi_ad9361: mmcm rst for plls
2016-05-04 13:42:12 -04:00
16a13b2023
library/axi_ad9361: add rst/locked to clock
2016-05-04 13:42:11 -04:00
1aac44b0d9
library: ad_*clk- rst/locked
2016-05-04 13:42:11 -04:00
d82ca5dc3c
library/common- altera variations
2016-05-04 13:42:11 -04:00
b6b68e9ab7
axi_jesd_gt: Split the constraint file
...
-split axi_jesd_gt_constr.xdc file in rx, tx and common constraint files
-updated tcl script
2016-05-04 19:32:06 +03:00
583bafd17a
axi_ad7616: Add a new register for IF_TYPE
...
Add an additional new read only register at 0x03 address for the interface type. This way the software can verify the actual interface mode.
2016-05-04 16:14:29 +03:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
3f5e1e1203
ad9361- dev_if module name change
2016-04-29 10:17:35 -04:00
89f5d2394e
altera- clock variations
2016-04-29 10:17:35 -04:00
243d3e6e41
ad9361- a10soc sdc files
2016-04-29 10:17:35 -04:00
aa2aa902bf
ad9361- a10soc updates
2016-04-29 10:17:35 -04:00
f411d29e30
ad9361- a10soc changes
2016-04-29 10:17:35 -04:00
3563c2212c
common/altera- removed dcfilt/mul
2016-04-29 10:17:35 -04:00
0260280db1
common/altera- data path
2016-04-29 10:17:35 -04:00
ed62101308
common/altera: primitives
2016-04-29 10:17:35 -04:00
779d014750
ad9361-common alt/xil interface
2016-04-29 10:17:35 -04:00
7ec4c00f9f
axi_ad7616: DMA is always ready
2016-04-29 16:36:33 +03:00
427f85959c
axi_ad7616: Fix the AXI stream interface
2016-04-29 16:34:34 +03:00
33199263e1
axi_ad7616: Delete burst_length register
...
This was an unnecessary feature of the hdl core.
2016-04-29 16:28:48 +03:00
d5d7c12f0e
axi_ad7616: Fix the register map
2016-04-25 11:36:39 +03:00
2ccdd426ec
axi_ad7616: Fix the rd_db_valid generation and do some cosmetic changes.
2016-04-25 11:28:22 +03:00
ad227c1af0
up_axi: Wait more to a valid read acknowledge.
2016-04-25 10:34:17 +03:00
e9b199959a
library/adcfifo- constraints update
2016-04-20 15:57:25 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
d7d8b2cf1c
axi_usb_fx3: Integrated actual GPIF II interface, with 2 address lines
2016-04-19 14:38:26 +03:00
e855ef38f4
axi_dacfifo: Initial commit
...
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 11:28:33 +03:00
42cd05ab19
ad_mem_asym: Add support for more ratios.
...
Supported ratios: 1:1/1:2/1:4/1:8/2:1/4:1/8:1
2016-04-19 11:18:30 +03:00
6fe41ebb08
axi_hdmi_tx: Upgrade hdmi clipping process
...
-added two registers that control the clipping ranges (0x01a and 0x01b)
-extend clipping process for all output data formats
2016-04-12 22:01:07 +03:00
69d721526a
util_dacfifo: Add constraints file
2016-04-12 13:21:50 +03:00
255b0ebd40
util_dacfifo: Add dac_xfer_out control
...
The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
b31cdac6bd
util_gmii_to_rgmii: Updated to 2015.4
...
The Xilinx interface changed its name from gmii_rtl_1 to gmii_rt_1
2016-03-23 10:14:18 +02:00
46eddd04be
library: port updates on mmcm
2016-03-22 12:50:59 -04:00
de4da6726b
axi_clkgen: port updates on mmcm
2016-03-22 12:50:59 -04:00
74408881c6
axi_ad9122: optional clock out control
2016-03-22 12:50:59 -04:00
65b2e51958
common/mmcm: add another clock
2016-03-22 12:50:59 -04:00
769fecbe00
axi_i2s_adi: Fixed clock association
2016-03-21 20:18:45 +02:00
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
6d277733d5
axi_spdif_rx: Fixed the clock association
2016-03-18 13:58:13 +02:00
28990e362a
axi_spdif_tx: Fixed the clock association
2016-03-18 13:31:06 +02:00
896c734792
Revert "foobar"
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This reverts commit a3cb8cac45
2016-03-18 13:23:02 +02:00
a3cb8cac45
foobar
2016-03-18 11:51:13 +02:00
665bfbc991
axi_ad7616: Add M_AXIS_READY_ENABLE parameter
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m_axis_ready can be driven by the DMA or can have a constant active state. By default is always one.
2016-03-15 18:38:55 +02:00
9b2a106aa0
axi_jesd_gt: changed clock and reset naming to be consistent with the other projects
2016-03-15 11:20:31 +02:00
06b7916303
axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:18:25 +02:00
ef05642e26
axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:14:05 +02:00
b3ed38107c
axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:12:45 +02:00
8ecf5edaf8
ad9122- pat modes
2016-03-14 11:14:29 -04:00
31cc91d1b9
adi_ip: Updated to 2014.4.2
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- automatically infer clocks, resets, axim_mm and axis interfaces
2016-03-14 15:14:18 +02:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
573146aa96
axi_ad7616: Fix the data width of the AXI stream interface
2016-03-10 16:38:53 +02:00
287770a201
axi_dmac: Fix tlast generation on AXI stream master
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For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-03-08 10:53:59 +01:00
2524f19ae0
Updated interfaces Makefile and Makefiles for the libraries that depend on it
2016-03-07 12:31:41 +02:00
583ef82fd0
ad9361- cmos mode
2016-03-04 10:39:48 -05:00
7a320a3d34
ad_lvds* - updates
2016-03-04 10:39:48 -05:00
7d2939be92
ad9361- cmos mode initial commit
2016-03-04 10:39:48 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
a8e9d72273
adc/dac - prefix parameters
2016-02-17 14:16:04 -05:00
e1c5d6a8f7
axi_ad9684: Fix constraint file
2016-02-12 14:38:59 +02:00
a747fad540
axi_ad9361: tx_valid must be controlled by the TDD controller
2016-02-12 14:33:34 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
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Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
0d67af370f
util_upack: Fixed problem when dac valid isn't continuous from the DAC
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In cases when the dac_valid_ from the DAC is not continuous, in some situations
there were two dac_valid pulses sent to the DMA.
2016-02-04 13:03:46 +02:00
3d3d1098b4
axi_ad7616: Default DATA_WIDTH is 8 bits
2016-01-28 16:02:01 +02:00
122667259f
ad7616_sdz: Update Make file
2016-01-28 14:48:44 +02:00
fbb0d368bf
axi_ad7616: Add support for parallel interface
2016-01-28 12:37:22 +02:00
cd43ebd8bc
axi_ad7616: The OP_MODE parameter is no longer required
2016-01-26 11:05:33 +02:00
2a17ce275c
axi_ad7616: Control inputs are controlled through GPIO
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The following control inputs are controlled through GPIO: reset_n, seq_en, hw_rngsel, chsel, crcen, burst and os.
2016-01-25 17:50:50 +02:00
4b962e8d72
spi_engine: The width of the counters depend on the current DATA_WIDTH
2016-01-20 15:44:06 +02:00
4cc69c0cac
axi_ad9684: Add Makefile
2016-01-19 18:32:11 +02:00
c865dbf353
axi_ad9680: Fix channel instantiation
2016-01-19 12:49:45 +02:00
df3eefdca1
axi_ad9434: Update constraint file
2016-01-19 12:43:05 +02:00
d1e638349b
ad_serdes_clk : The reference clock selection line should by tied to 1
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Just the CLKIN1 is used in the MMCM.
2016-01-19 11:18:00 +02:00
c6cfd1a2b6
axi_ad9684: Initial check in
2016-01-19 11:13:45 +02:00
4f2b999999
axi_ad9680: Q_OR_I_N is not used in this channel
2016-01-13 16:26:22 +02:00
838b558176
axi_ad9434: Fix adc_status
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adc_status was not driven by anything. Should be driven by adc_status_m1.
2016-01-13 12:21:42 +02:00
2dcd9136aa
axi_ad6676: Delete confusing comment
2016-01-13 10:20:18 +02:00
c29dd8fad5
axi_ad7616: Fix Makefile
2015-12-21 19:39:58 +02:00
0b55325db9
axi_ad7616: Fix IP packaging script
2015-12-21 19:39:14 +02:00
17e7d1b86f
ad7616: Add Makefiles
2015-12-21 17:09:42 +02:00
8ae9de8fba
axi_ad7616: Update core
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+ Both the data width and number of SDI lines are configurable
+ SER1W line is hardware configurable, it was removed from the IP
+ Add 'Hardware mode' support for the controller
2015-12-14 16:00:56 +02:00
4e57170384
spi_engine: Update SPI Engine frame work
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+ data width and number of SDI lines are configurable
+ axi_spi_engine module can have two different type of memory map interface (S_AXI or UP)
2015-12-14 15:57:54 +02:00
29a0f27cd1
ad_edge_detect: Add a flop to output, reset is active high
2015-12-14 15:40:29 +02:00
4c2d08a9be
ad9152: altera syntax error
2015-12-11 12:49:00 -05:00
bc93910ee5
ad9152: qsys updates
2015-12-10 16:04:10 -05:00
ff1d98a0c7
ad9144: duplicate include
2015-12-10 16:02:35 -05:00
ce906989d5
ad9152: qsys ip
2015-12-10 09:46:31 -05:00
12c95b059d
ad_tdd_control: Remove tdd_enable_synced control line
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For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
5cf45b2978
axi_clkgen: Added phase related parameters
2015-12-02 18:50:23 +02:00
36febf8591
Merge branch 'master' into dev
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Conflicts:
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_dmac/Makefile
library/axi_dmac/axi_dmac_constr.ttcl
library/axi_dmac/axi_dmac_ip.tcl
library/common/ad_tdd_control.v
projects/daq2/common/daq2_bd.tcl
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms2/zc706pr/system_project.tcl
projects/fmcomms2/zc706pr/system_top.v
projects/usdrx1/common/usdrx1_bd.tcl
This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
667e49fe41
library: Axi_clkgen, added register for controlling the source clock.
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Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
2015-11-25 11:16:32 +02:00
df58646925
util_adcfifo: Updated altera interface
2015-11-25 10:20:06 +02:00
593c486168
ad_tdd_control: The state machine goes from OFF to ON, when a valid sync is received
2015-11-24 15:15:53 +02:00
c70be7391f
ad_tdd_control: Avoid unnecessary reset on control lines
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No need to reset for tdd_last_burst, it's value depends on the tdd_burst_counter.
2015-11-24 15:13:18 +02:00
ee0617661e
axi_ad9680: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:45:12 +02:00
f51871c1e4
axi_ad9144: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:44:07 +02:00
76823f95fa
axi_ad9250: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:39:55 +02:00
275ec3d3a8
axi_ad9361: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:21:08 +02:00
250f3c917b
axi_ad9361: Removed old signals from the altera device interface module
2015-11-24 11:20:35 +02:00
fb269f7a29
util_cpack: Updated altera interfaces
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- DMA side, simplified naming
- ADC side, added FIFO conduit per channel
2015-11-24 11:18:18 +02:00
e6de2ade78
util_upack: Updated altera interfaces
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- DMA side, simplified naming
- DAC side, added FIFO conduit per channel
2015-11-24 11:17:02 +02:00
c5ff1674c6
axi_dmac: Updated fifo interfaces for easier connectivity
2015-11-24 11:08:28 +02:00
e5d2f5be06
util_upack: Cosmetic changes
2015-11-24 10:55:10 +02:00
985f2ca020
library: ad_rst, added comment so that the registers are not minimized away
2015-11-24 10:33:38 +02:00
bdf9754971
util_tdd_sync: Sync signals output reg is a false path source
2015-11-17 09:42:05 +02:00
9ba8c059ce
ad_tdd_sync: Fix reset value of the pulse_counter
2015-11-13 18:31:24 +02:00
d6eae81bc1
axi_ad7616: Add the control module to the core, finish up SPI integration
2015-11-13 18:14:21 +02:00
3c27b3a4c5
ad_lvds_in: Add single ended option
2015-11-13 12:13:09 +02:00
952a491f59
axi_ad7616: Add spi engine to the core
2015-11-12 16:12:16 +02:00
b17fec689e
ad_tdd_control: An active sync pulse can NOT be a reset for the control lines
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By reset the control lines (RF, VCO and DP) on an active sync pulse, can cause glitches on the ENABLE/TXNRX lines. The sync pulse resets just the TDD counter.
2015-11-11 11:13:33 +02:00
fc0f4bc414
axi_ad9361: Delete the old sync generator from the core
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+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
a290611c09
util_tdd_sync: Initial commit
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A synchronization signal generator for AD9361 running on TDD mode.
If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
2015-11-11 10:46:11 +02:00
e4927887fd
spi_engine_offload: Add sync_bits to the IP files list
2015-11-10 13:35:15 +02:00
229cd079b9
spi_engine: Fix to support multiple SDI lines
2015-11-10 13:34:29 +02:00
64d1948ea0
axi_ad7616: Initial commit
2015-11-10 13:32:56 +02:00
5cc97c78d3
Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries
2015-11-10 09:32:50 +02:00
e7fd964874
axi_clkgen: Added a second input clock option
2015-11-06 17:55:29 +02:00
839e76996f
axi_gpreg: added constraints
2015-11-05 11:28:37 -05:00
482b740229
axi_gpreg: add buffer enable
2015-11-05 11:28:35 -05:00
66d4f8fd58
util_gtlb: output receive/transmit clocks
2015-11-05 11:28:34 -05:00
28bfeb442c
util_gtlb- syntax error fixes
2015-11-05 11:28:31 -05:00
6d28a92b5b
util_adcfifo: Added altera initial constraints file
2015-11-04 13:34:52 +02:00
e8b84b3662
axi_dmac: Updated axis destination / source ports for altera component
2015-11-04 13:33:41 +02:00
de53a61902
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow
...
Added altera component
2015-11-04 13:31:50 +02:00
6cfc13a9dd
common: Allow for the memory to be also symetrical
2015-11-04 13:28:02 +02:00
ad1cef1441
axi_gpreg: compile fixes
2015-11-03 14:29:00 -05:00
c8019b69fd
axi_gpreg- added
2015-11-03 14:28:59 -05:00
88f247a1de
util_gtlb: use gpio
2015-11-03 14:28:57 -05:00
cf58110a98
Merge branch 'dev' into dev_ad7616
2015-11-03 14:07:48 +02:00
acd9efc528
axi_hdmi_tx: Add parameter to configure the output clock polarity
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In order to maximize the window where it is safe to capture data we ideally
want to launch data on the opposite edge to which it is captured. Since the
edge on which data is captured depends on the connected device add a
parameter that allows to configure the launching edge.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
a147acd791
spi_engine: Add support for multiple SDI lines.
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By changing the parameter called SDI_DATA_WIDTH the spi framework can support multiple SDI lines.
The supported number of SDI lines are: 1, 2, 3 and 4.
2015-11-02 18:42:55 +02:00
88568c21e1
util_gtlb: updates for latest axi_jesd_gt
2015-10-30 18:47:36 -04:00
2b6ae00a44
library: add mfifo
2015-10-27 14:52:02 -04:00
f1ed27105f
library/common- reset fix
2015-10-23 14:32:35 -04:00
32b3cfd8b9
axi_usb_fx3: Initial commit of the core with interface stub
2015-10-23 13:27:00 +03:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
6fb56079ee
library/util_gtlb: Add Makefile
2015-10-16 13:58:01 +03:00
8ecdb4a4ca
library/tdd_control: Add common registers to the register map and fix init value of a register
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+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
44568f1f64
util_jesd_gt: bad idea, it is needed for ipi
2015-10-15 11:13:08 -04:00
a6ff1b13fc
util_jesd_gt- remove unused parameters
2015-10-15 10:46:07 -04:00
c9a5057b93
library/prcfg : Split data bus to channels
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Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
a753d506c5
axi_mc_controller: Removed channels, as no data needs to be streamed to DMA
2015-10-09 13:54:03 +03:00
694dbd3259
axi_mc_controller: Updated constraints
2015-10-09 13:53:13 +03:00
7c3646e863
axi_mc_current_monitor: Removed stub channel
2015-10-09 13:52:14 +03:00
99e6240126
axi_mc_current_monitor: Updated constraints
2015-10-09 13:51:15 +03:00
d19d9c8fbc
axi_mc_speed: Corrected maximum number of channels
2015-10-09 13:50:25 +03:00
ce01185348
axi_mc_speed: Updated constraints
2015-10-09 13:50:08 +03:00
96d363849e
ad_dds: Registered dds_scale so that Vivado can optimally map the dsp block
2015-10-09 13:43:14 +03:00
df8ac2e726
axi_ad9671: Updated constraints
2015-10-09 13:15:55 +03:00
03b225a802
axi_ad9671: Fixed synchronization mechanism
2015-10-09 13:15:12 +03:00
8321d5a4fb
util_dacfifo: Update read out method
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Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
2015-10-08 17:13:12 +03:00
1ebd38c514
util_dacfifo: Update read out method
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Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
2015-10-08 16:50:36 +03:00
cd9754afbe
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
f3ffd5a63f
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
2b894bc13e
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
5c3f90a676
up_gt: separate pll resets to tx/rx
2015-10-02 13:58:30 -04:00
ba70c7a4ea
ad9144- ip updates
2015-09-30 11:37:10 -04:00
54fcf06eed
ad9152- ip updates
2015-09-30 11:34:09 -04:00
81a1c21553
util_pmod_adc: Reset line changed to active low reset.
2015-09-30 12:33:46 +03:00
97a9ecfc9a
axi_hdmi_rx: Update constraint file and fix reset line
2015-09-29 18:49:30 +03:00
b765be568f
up_gt_channel: Delete the register, which stores transceiver type
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Transceiver type is stored in axi_jesd_gt/up_gt only.
2015-09-29 14:23:42 +03:00
cffb2e6226
up_gt_channel: Move the VERSION register to up_gt_channel, in order to preserve its address
2015-09-29 14:19:52 +03:00
a0ac0e912b
up/ad_gt_common/channel: Cosmetic changes
2015-09-29 14:16:24 +03:00
dff6c0df01
axi_ad9652: Updated with the latest constraints
2015-09-28 11:29:07 +03:00
c03983ca54
ad_tdd_sync/control: Update TDD logic
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+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
2015-09-25 19:11:23 +03:00
07e2d281c0
Make: Update Make files
2015-09-25 19:11:21 +03:00
884973fdbb
util_dacfifo: Cosmetic changes
2015-09-25 17:41:44 +03:00
2816812e0a
axi_ad9625: Updated constraints and added adc reset port
2015-09-25 17:16:31 +03:00
37a4e976d6
axi_ad6676: Updated constraints
2015-09-25 17:02:42 +03:00
061f468fb1
axi_ad9250: Update library
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- added adc reset port
- addded common constraints
2015-09-24 19:10:19 +03:00
ebaebc54f7
axi_ad9680: Clock ratio is indicating a sampling clock ratio
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The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:29 +03:00
9ad59c58db
axi_ad9234: Clock ratio is indicating a sampling clock ratio
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The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:18 +03:00
0b08250261
axi_ad9152: Clock ratio is indicating a sampling clock ratio
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The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:19:08 +03:00
892755c084
axi_ad9144: Clock ratio is indicating a sampling clock ratio
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The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:18:48 +03:00
5e082be963
axi_ad9680: Clock ratio is indicating a sampling clock ratio
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The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:14:01 +03:00
edb94ada8b
axi_ad9234: Clock ratio is indicating a sampling clock ratio
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The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:13:20 +03:00
d45f49c062
axi_ad9152: Clock ratio is indicating a sampling clock ratio
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The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:12:36 +03:00
0a4f43efea
axi_ad9144: Clock ratio is indicating a sampling clock ratio
...
The software can use this data to calculate the effective sampling clock, independent of the interface type.
2015-09-24 11:11:29 +03:00
900db3d8ed
util_wfifo: Fix reset related timing violation
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The memory instance reset connected to ground, rather than connect to dout_rstn.
2015-09-23 16:36:33 +03:00
516c59523d
util_wfifo: Cosmetic changes.
2015-09-23 16:36:31 +03:00
568333bbfc
axi_dmac: Fix typo on ./bd/bd.tcl
2015-09-23 15:51:50 +03:00
aa608e3907
axi_ad9467: Update constraints
2015-09-23 14:26:57 +03:00
0411ad2386
axi_ad9434: Update constraints
2015-09-23 14:26:55 +03:00
ab8256cf92
ad_tdd_control: Redesign the state machine to prevent timing failure.
2015-09-22 10:33:50 +03:00
cd93beb10f
util_axis_fifo: Remove m_axis_addr_next output from the address modules
...
Remove m_axis_addr_next output from the address modules since it is no
longer used.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
5c22e622de
axi_dmac: Fix width for dest response FIFO
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The width of the dest response FIFO is 1 bit not 3 bits.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
cfd57fc462
axi_dmac: Drive unused interface output ports with const value
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Drive all output pins of the disabled interfaces with a constant value.
This avoids warnings from the tools about not driven output ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
fed14cf613
axi_dmac: Mark unused output ports explicitly as unconnected
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Mark all unused output ports explicitly as explicitly. This makes it clear
that they are left unconnected on purpose and avoids warnings from the
tools about unconnected ports.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
a7f4b11624
axi_dmac: Beautify IPI GUI
...
Group the axi_dmac parameters by function and provide a human readable name
for the IPI GUI. This makes it easier to understand what parameter does
what when using the IPI GUI to configure the core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
5b5a4707d2
axi_dmac: Add validation values to IPI package
...
Add validation values for the different configuration parameters. This
enables the tools to check whether the configured value is valid and avoids
accidental misconfiguration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
104e49d515
axi_dmac: Remove unused address bits on AXI-Lite bus
...
The address width for the AXI-Lite configuration bus for the core is only
14 bit. Remove the upper unused bits from the public interface.
This allows infrastructure code to know about this and it might be able to
perform optimizations of the interconnect based on this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
89ceae3757
axi_dmac: Move m_axi_src interface clock and reset next to other signals
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Move the clock and reset signals of the m_axi_src interface next to the
other signals in the module definition.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:24 +02:00
5aa11feb48
axi_dmac: Change BRAM REGCEB constraint to set_false_path
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According to the documentation when using a BRAM block in SDP mode the
REGCEB pin is not used and should be connected to GND. The tools though
when inferring a BRAM connect REGCEB to the same signal REGCEA. This causes
issues with timing verification since the REGCEB pin is associated with the
write clock whereas the REGCEA pin is associated with the read clock.
Until this is fixed in the tools mark all paths to the REGCEB pin as false
paths.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:22 +02:00
4c51224696
axi_dmac: Configure AXI master bus properties according to core configuration
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Configure the maximum burst size as well as the maximum number of active
requests on the AXI master interfaces according to the core configuration.
This allows connected slaves to know what kind of requests to expect and
allows them to configure themselves accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:19 +02:00
12fc6d1672
axi_dmac: Indicate that the core does not issue narrow AXI bursts
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The axi_dmac core does not issue narrow AXI bursts. Indicate this by
setting the SUPPORTS_NARROW_BURST property to 0 on both AXI master
interfaces.
This allows connected slaves to know that they will not receive narrow
bursts, which allows them to disable support for it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:18 +02:00
5f307f862f
axi_dmac: Use sane defaults for the AXI protocol type
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The axi_dmac core generates requests which are both AXI3 and AXI4
compliant. This means it is possible to connect it to both a AXI3 or AXI4
slave port without needing a AXI protocol converter. Unfortunately it is
not possible to declare a port as both AXI3 and AXI4 compliant, so the core
has the C_DMA_AXI_PROTCOL_SRC and C_DMA_AXI_PROTOCOL_DEST parameters, which
allow to configure the protocol type of the corresponding AXI master
interface. Currently the default is always AXI4.
But when being used on ZYNQ it is most likely that the AXI master interface
of the DMAC core ends up being connected to the AXI3, so change the default
to AXI3 if the core is instantiated in a ZYNQ design.
The default can still be overwritten by explicitly setting the
configuration property.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:17 +02:00
f079b2193a
axi_dmac: Add support for auto-detecting asynchronous clock configuration
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Add support for querying the clock domains of the clock pins for the
axi_dmac controller. This allows the core to automatically figure out
whether its different parts run in different clock domains or not and setup
the configuration parameters accordingly.
Being able to auto-detect those configuration parameters makes the core
easier to use and also avoids accidental misconfiguration.
It is still possible to automatically overwrite the configuration
parameters by hand if necessary.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:15 +02:00
19f7d8500c
adi_ip.tcl: Add support for adding bd files to a core
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bd files can be used to automate certain tasks in IP integrator when the
core is instantiated. Add a helper command for adding such files to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:14 +02:00
39320ef48b
axi_dmac: Fix source pause signal
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For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:13 +02:00
91bb54467b
axi_dmac: Generate per core instance constraint file
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When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.
This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.
This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:12 +02:00
0f5f21eec2
adi_ip.tcl: Add helper function to add TTCL files to a core
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Add a helper function which allows to add TTCL templates files to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:10 +02:00
46808c4c41
util_wfifo: Changed some reset for several registers from asynchronous to synchronous for better integration with the FIFO
2015-09-16 18:55:47 +03:00
6804f3377a
axi_ad9643: Updated core with latest constraints
2015-09-16 15:49:13 +03:00
5347c058df
axi_ad9122: Updated core with latest constraints
2015-09-16 15:48:33 +03:00
884f45c81d
common library: Registered dc_filter and iq_correction coefficients
2015-09-16 14:24:18 +03:00
052860cbc3
axi_dmac: Fix source pause signal
...
For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-16 11:02:08 +02:00
5af371db6b
axi_dmac: Generate per core instance constraint file
...
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.
This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.
This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-15 19:54:33 +02:00
522f30ce21
adi_ip.tcl: Add helper function to add TTCL files to a core
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Add a helper function which allows to add TTCL templates files to a core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-15 19:00:56 +02:00
7c896ba5f8
axi_ad9361: Fixed constraints definition
2015-09-14 18:20:30 +03:00
67ffeb18e8
axi_ad9739a: Updated core with latest constraints
2015-09-11 14:04:33 +03:00
e33403816c
axi_ad9265: Updated core with latest constraints
2015-09-11 11:26:28 +03:00
5bc16159fa
ad_tdd_sync: The resync will reset all the control lines
2015-09-10 11:28:36 +03:00
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
85ffc25ec5
ad_tdd_sync: Update the synchronization logic
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The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
5a566b9e5d
ad_tdd_control: Add delay compensation for the control lines
2015-09-09 12:24:26 +03:00
6acb350ee5
axi_dmac: Update for axi_dmac_constr.xdc
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Parameter called 'processing_order' default value is 'late'. No need to specify it at process call.
2015-09-09 12:08:35 +03:00
381ffd43c1
gtlb- remove pn test-reset
2015-09-08 13:52:33 -04:00
9bef9742b7
jesd_gt- cosmetic changes
2015-09-03 16:16:24 -04:00
84ced344d9
gtlb- up-sync make w1c
2015-09-03 16:16:22 -04:00
e0b5044aa3
axi_dmac: Disable dummy AXI ports for Xilinx IPI
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The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.
The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
2a09257f38
pzslb- updates - wip
2015-08-31 15:41:28 -04:00
c1b01517f8
util_gtlb: added
2015-08-31 15:41:22 -04:00
1e5afdd535
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
6cf7eb5ad4
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
4554eb03b0
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
704385a8dc
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
a33c08725b
axi_hdmi_tx- altera ip changes
2015-08-28 13:48:33 -04:00
1cd3435147
up_delay_cntrl- cosmetics
2015-08-28 13:16:18 -04:00
8fddf983d2
up_hdmi_tx- common/generic instance names
2015-08-27 13:17:06 -04:00
88f806f584
ad9361- alt io matching
2015-08-27 11:55:24 -04:00
74e72021f7
ad9361- ensm through dev-if
2015-08-27 11:41:53 -04:00
664ef017bb
ad9361- ensm through dev-if
2015-08-27 11:41:52 -04:00
29b0ec0378
ad9361- ensm through dev-if
2015-08-27 11:41:51 -04:00
d82d37c23f
ad9361- ensm through dev-if
2015-08-27 11:41:49 -04:00
2259b6cbf7
ad9361- ensm through dev-if
2015-08-27 11:41:48 -04:00
20ee10ea46
common/ad_lvds_out- add single ended
2015-08-27 11:41:47 -04:00
c56b534ec0
dacfifo- remove interfaces
2015-08-27 11:18:00 -04:00
ba64de228e
ip-constr- register name changes
2015-08-27 11:18:00 -04:00
f3410a7db1
xpack- remove useless interfaces
2015-08-26 14:12:14 -04:00
b0d22d323a
ad9361- axi-clock definitions
2015-08-26 14:11:43 -04:00
4655af7bf6
2015.2 updates
2015-08-26 11:33:44 -04:00
18f688514b
2015.2 updates
2015-08-26 11:33:37 -04:00
7780b3a3a2
2015.2 updates
2015-08-26 11:33:27 -04:00
7b858bc5ad
Revert commit 6b99ce
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Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
386cc74ab4
util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl
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Fix port names at the 'port_maps' attribute of the adi_add_bus process call.
2015-08-25 09:41:34 +03:00
Rejeesh Kutty
Istvan Csomortani
AndreiGrozav
Shrutika Redkar
Adrian Costina
Lars-Peter Clausen
Matthew Fornero
István Csomortáni
Dragos Bogdan