SPI Engine: create inverted CS mode
Add a CS Invert Mask instruction for selecting the polarity of
the Chip Select pins.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Rename "idle bus" to "bus available" per specification:
* Tune it to require < 1us.
Rename "IBI auto" to "IBI listen":
* Clarify that the controller is listening for IBI's:
* Explain that this field should be set.
* Fix for known IBI's DA with IBI disabled.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
This commit implements Cache Coherency through dedicated parameters.
The AxCACHE/AxPROT parameters are automatically set to the most commonly
used values unless otherwise specified. Their default values are:
AxCACHE = CACHE_COHERENT ? 4'b1111 : 4'b0011
AxPROT = CACHE_COHERENT ? 3'b010 : 3'b000
If Cache Coherency is enabled, the AxCACHE/AxPROT values can be changed
to support systems with different caching policies.
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Unified the ad7606x_fmc project, where both the serial and the parallel interface are implemented.
---------
Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
1. Add intermediary data_src_select register to control output selection
between DMA and RAW. The switch RAW->DMA is not made until DMA has valid
data; the switch DMA->RAW is not made until overwrite_enable is 1
regardless of dac_valid.
2. When overwrite is enabled, set the intermediary DMA register data_r
to the RAW value.
This fixes an issue of the logic analizer that caused the last sample of a DMA
transfer to be visible at the next DMA transfer.
Signed-off-by: dumitruceclan <dumitru.ceclan@analog.com>
This change will fix the timing closure for designs where the external
clock is not a submultiple of the s_axi_clk.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
New features:
1. External sync force the phase align. The external sync was used to align
the phases of enabled pwms, but only after being armed by a
load_config signal toggle.
This feature lets the user decide between using load_config to
arm and wait for a neg-edge of sync or automatic phase align trigger
on the ext_sync neg-edge.
2. Force align. Lets the user chose between immediately stopping the
active pulses and realigning them, or waiting for all running pulse
periods end, before realigning.
3. Start at sync. When this feature is activated, the pulses will start immediately
after the trigger event. Otherwise, each pulse will start after a period
equal to the one for which it is set.
4. Use parameters to set the default status after reset of the
- soft reset
- start at sync
- force align
- ext sync align
Update regmap.
Fixes:
1. The polarity on disabled channels was staying high instead of low.
2. Fix 0 and 100 proc duty cycle configuration.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
Intermittently DAC channel data is 0 after multiple new buffers.
Due to the low sampling rate and DMA flushing, it happens that the
transfer SM gets stuck in flushing mode right before the transmission
should start.
Another frequent issue happens when a new transmission is started.
A buffer must be pushed independently for each channel because of
separate DMAs.
After the first buffer is pushed the Linux driver deactivates the
start_sync flag. Not knowing if the other channel/buffer will be
active/pushed. The start_sync will be re-enabled with the second buffer.
The issue was that the SM of the first buffer went one step further
before the push if the second buffer,not being stopped by the
start_sync.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Add I3C Controller IP with required I3C features support.
Uses IRQ based DAA.
Supports speeds at 100MHz clk: 12.50MHz, 6.25MHz, 3.12MHz, 1.56MHz
Basic IBI support with/without MDB.
Compatible with AMD Xilinx and Altera FPGAs.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Lattice tools give error for using blocking assignments at one side
and non blocking in the other.
Signed-off-by: Villyam <Vilmoscsaba.Jozsa@analog.com>
Revert AXI bus signals back to upper case on SPI Engine Offload IP,
changed on e2ca5a991a.
Fixup signals from sd*_data_* to sd*_* for spi_engine_ctrl interface.
Non-breaking mistake, but added warnings to the IP.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* SPI Engine: Add registers for Offload memory and FIFO sizes
Adds registers at dword 0x04 and 0x05, respectively allowing software
to get the sizes of the Offload Module memories (command and sdo) or
the sizes of the FIFOs on the AXI regmap.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Use tcl script instead of static xmls for the interface.
Easier to maintain and are not gitignored.
Rename spi_master to spi_engine because every interface should be
prefixed by the IP name; in this case, spi_engine.
Also, remove interface/*.sv files on make clean and git ignore them.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* Value 24 was wrongfully set for parameter LENGTH_WIDTH, because
it is not among the valid values, which are 28, 29, ..., 34. Set '28'
to be the default value
* Vivado Tcl somehow didn't accept the old expression set for
calculating the HBM_SEGMENTS_PER_MASTER parameter, so it was changed
accordingly to work. Dropped "expr", ".0" and "int ()" parsing and now
it works
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
* SPI Engine: fix early sdi data clear
In case an SPI read was immediately followed by a cs assert, the sdi
register was being cleared one cycle too soon, so that the data being
passed on was always 'b0.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Previous level-based trigger could cause issues in some low
sampling rate setups. This commit changes it to edge-based.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
The lack of the create_xgui_files causes Vivado to exit with an error
when running multiple Vivado instances (parallel make case)
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Set validation ranges for DATA_WIDTH and NUM_OF_CS for the expected
min/max values in the verilog source code.
Also, fix swapped description for CPHA in the documentation.
Signed-off-by: Carlos Oliveira <caosjr8@gmail.com>
Previously when issuing a load_config, each pwm channel
was stopped in its tracks and waited for an external sync,
if that was active, or load_config release.
The desired behaviour is to wait for the pwm channels to finish
their events from the current period, before a new aligned start.
Also, the first positive edge of each pulse was initiated only
in the second pwm channel period.
This niche behaviours have not affected any functionality in the
long term alignments for current setups.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
When leaving the offset equal to zero for a pwm
channel. That pwm channel was not waiting for all
channels to get in sync after a load config.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Drop shell for loops in favor of makefile pattern rules,
so make can run targets in parallel using -j.
This doesn't affect Vivado's own settings.
As a benchmark, 12th Gen Intel(R) Core(TM) i9-12900H 5GHz(max):
$ make -C projects/adrv9009/zcu102/ clean-all
$ time make -C projects/adrv9009/zcu102/ -j$CORES lib
CORES=1:
real 9m27.223s
user 9m2.556s
sys 0m32.358s
CORES=8:
real 1m54.639s
user 16m26.512s
sys 1m2.317s
i.e. about 5 times faster to build IP core dependencies.
Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
1. Simplify the control logic by adding a state machine.
The improvements are on code readability and reliability.
2.Add a flush feature which can be used to clean the data from the DMA fifo.
This is useful when the DMA is programmed in cyclic mode and
data transmission is stopped by dma_transfer_suspend flag
The software intervention is reduced at setting the flag(dma_flush_en).
Flushing can also be done when activating the raw value with dma_flush_en active.
3. Add raw value support. Through this changes a user can set
the dac output to a fixed predefined value in the following two cases:
1. direct, without using the dma.
2. with dma, as a hold value. The fixed value will be kipped after a cyclic
buffer is stopped by axi_dac_interpolate, through dma_transfer_suspend
register/signal.
The raw value ca be set and transmitted independently on each channel.
The predefined value is stored in reg 0x19(0x64). For more details se
the documentation available at
https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate
axi_dac_interpolate - Remove last sample hold control
axi_ad9963 - Remove last sample hold control and set as default the
last sample hold functionality plus code optimization changes.
This commit introduces a different interface to submit transfers, using
DMA descriptors.
The structure of the DMA descriptor is as follows:
struct dma_desc {
u32 flags,
u32 id,
u64 dest_addr,
u64 src_addr,
u64 next_sg_addr,
u32 y_len,
u32 x_len,
u32 src_stride,
u32 dst_stride,
};
The 'flags' field currently offers two control bits:
- bit 0: if set, the transfer will complete after this last descriptor
is processed, and the DMA core will go back to idle state; if cleared,
the next DMA descriptor pointed to by 'next_sg_addr' will be loaded.
- bit 1: if set, an end-of-transfer interrupt will be raised after the
memory segment pointed to by this descriptor has been transferred.
The 'id' field corresponds to an identifier of the descriptor.
The 'dest_addr' and 'src_addr' contain the destination and source
addresses to use for the transfer, respectively.
The 'x_len' field contains the number of bytes to transfer,
minus one.
The 'y_len', 'src_stride' and 'dst_stride' fields are only useful for
2D transfers, and should be set to zero if 2D transfers are not
required.
To start a transfer, the address of the first DMA descriptor must be
written to register 0x47c and the HWDESC bit of CONTROL register must
be set. The Scatter-Gather transfer is queued similarly to the simple
transfers, by writing 1 in TRANSFER_SUBMIT.
The Scatter-Gather interface has a dedicated AXI-MM bus configured for
read transfers, with its own dedicated clock, which can be asynchronous.
The Scatter-Gather reset is generated by the reset manager to reset the
logic after completing any pending transactions on the bus.
When the Scatter-Gather is enabled during runtime, the legacy cyclic
functionality of the DMA is disabled.
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
Fixed wrong behaviour on chip select instruction:
- previously, a sleep time happened before the chip select change
- the intended behaviour was for another sleep time, of equal amount, to happen after the chip select change as well
- additionally, the counter logic implementation was creating an additional factor of 2 on the sleep time
All of the above points were fixed. The changes introduced also fix another issue where the sleep instruction was likewise happening with a duration larger than intended by a factor of 2
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
The axi_ad4858 IP core is design as the HDL interface for the AD4858 ADC.
Features:
- AXI based configuration
- LVDS and CMOS support
- Configurable number of active data lines (CMOS - build-time configurable)
- Oversampling support
- Supports packet formats 0,1,2 or 3
- CRC check support
- Real-time data header access
- Channel based raw data access(0x0408)
- Xilinx devices compatible
Documentation at https://wiki.analog.com/resources/fpga/docs/axi_ad4858
The custom interface IP for AD3552R DAC has more operation capabilities:
- 8b register read/write SDR/DDR
- 16b register read/write SDR/DDR
- data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate)
- selectable input source : DMA/ADC/TEST_RAMP
- data out clock(SCLK) has clk_in/8 frequency when the converter is configured and clk_in/2 when the converter is in stream mode
- the IP reference clock (clk_in) can have a maximum frequency of 132MHz
- the IP has multiple device synchronization capability when the DMA is set as an input data source
Signed-off-by: PopPaul2021 <Paul.Pop@analog.com>
LBFFilho
Ionut Podgoreanu
Jorge Marques
AndreiGrozav
bluncan
PIoandan
dumitruceclan
Jorge Marques
IstvanZsSzekely
Villyam
Iulia Moldovan
caosjr
Alin-Tudor Sferle
Liam Beguin
Stanca Pop
PopPaul2021