laurentiu_popa
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8d0b6ba486
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projects: Update incomplete/inaccurate readmes
Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
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2023-07-31 09:35:39 +03:00 |
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laurentiu_popa
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e8b583802a
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projects: Update readmes initial commit
Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
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2023-07-31 09:35:39 +03:00 |
Iulia Moldovan
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c9a7d4d927
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Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2023-07-25 15:22:26 +03:00 |
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Iulia Moldovan
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1cac2d82e1
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Add copyright and license to .xdc files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2023-07-25 11:03:02 +03:00 |
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Iulia Moldovan
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28c06d505f
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Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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2023-07-11 15:17:41 +03:00 |
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laurent-19
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2ae09c9808
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Check guidelines. Remove redundancies
* Removed empty/commented lines
* Regenerated Makefiles
* Removed redundancies adc channels data width
* Set data width 32-bit: max resolution and CRC header
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
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2023-03-29 15:08:07 +03:00 |
Stanca Pop
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ee30c64923
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projects/ad4134_fmc: Initial commit add support
* Updated reference design: spi trigger, ODR parameters
- enabled ext_clk for PWM to use 96 MHz spi clk
- mofified PWM channels used:
- ch1: ODR - 850 ns period, 130 ns high time
==> max fODR = 1.18 MHz
- ch0: trigger - 850 ns period, 30 phase shift
==> 10 ns between falling ODR rising DCLK
- spi offload trigger signal: PWM trigger used
* Moved mem_interconnect to hp1
* Added dclkio GPIO
* Updated bd SPIE hierarchy, see library/spi_engine.tcl
Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
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2023-03-29 15:08:07 +03:00 |