pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Iulia Moldovan	1cac2d82e1	Add copyright and license to .xdc files Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>	2023-07-25 11:03:02 +03:00
LIacob106	d4126739b4	projects: remove hardcoded div_clk from xcvr	2021-10-27 12:11:22 +03:00
hotoleanudan	1c208c01d6	ad9656:Add reference design for the ad9656 eval board (#494 ) Added reference design for the ad9656 evaluation board coupled with the zcu102 carrier board. The JESD204 communication link that transfers data from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1, F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>	2020-10-06 09:53:40 +03:00

Author

SHA1

Message

Date

Iulia Moldovan

1cac2d82e1

Add copyright and license to .xdc files

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>

2023-07-25 11:03:02 +03:00

LIacob106

d4126739b4

projects: remove hardcoded div_clk from xcvr

2021-10-27 12:11:22 +03:00

hotoleanudan

1c208c01d6

ad9656:Add reference design for the ad9656 eval board (#494 )

Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>

2020-10-06 09:53:40 +03:00

3 Commits (fc2437a83a239f50b3a7fccfd59e5cbaad9c0fc0)