1d6ddacfd6
axi_ip_constr: Fix constraints
...
The filter for CDC registers were too generic, and a few non-CDC
register were set as asynchronous register.
2017-02-27 16:25:09 +02:00
2da7dd4079
axi_ip_constr: Update constraints
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Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-23 11:33:25 +02:00
c0a2ef1ac4
library- altera power up warnings
2016-12-20 16:18:15 -05:00
a00d9870be
axi_ip_constr: Fix constraints
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Modify a contraint for a false path, so it will be applied to
up_delay_cntr module too.
2016-12-16 12:01:38 +00:00
ba64de228e
ip-constr- register name changes
2015-08-27 11:18:00 -04:00
041be729f6
common/ip-constrs- uniform simple constraints will do
2015-08-13 13:03:51 -04:00
e2f4a4c5cf
library: make preset registered for timing paths
2015-06-10 13:41:41 -04:00
Istvan Csomortani
Rejeesh Kutty