pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Istvan Csomortani	f86ae28e50	spi_engine/data_reorder: Initial commit In case of multiple SDI (MISO) lanes, the samples arrives in a parallel fashion. For example in case of 4 MISO line, at the first latching clock edge 4 bits of a sample will be saved, one bit into each shift register. The data reorder module reconstruct the incoming samples from the AXI stream of the offload module.	2021-10-18 16:13:31 +03:00

Author

SHA1

Message

Date

Istvan Csomortani

f86ae28e50

spi_engine/data_reorder: Initial commit

In case of multiple SDI (MISO) lanes, the samples arrives in a parallel
fashion. For example in case of 4 MISO line, at the first latching clock
edge 4 bits of a sample will be saved, one bit into each shift register.

The data reorder module reconstruct the incoming samples from the AXI
stream of the offload module.

2021-10-18 16:13:31 +03:00

1 Commits (fcb16daf5b16ad7c1838c4ff815f7eafab796071)