Commit Graph

8 Commits (fce0491ad718ffb358e2c47c03a64d842a370206)

Author SHA1 Message Date
Jorge Marques 4d676ca25a
docs: Update README, misspelings, and improvements
Update docs instructions in the README.md to recommend building the libraries before generating the documentation.
Fix misspellings in the SPI Engines.
Use hashlib to gen the reproducible ids, so these elements won't be committed at every build in the gh-pages branch.
Get username from environment variable, to use in the symbolator local installation path, dismissing user interaction for this.
Use modelParameter to extract the type from ip-xact parameters without the format field, and improve formatting.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-10-06 09:23:50 -03:00
Jorge Marques 303b3a0eeb docs: add check for signals/bus
Signals/buses declared in the docs that does not exist in the
components.xml files will raise a warning.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00
Jorge Marques 55d4215f45 README.md: header, docs info; docs: license, fixes
Add documentation info to the README.md
At adi_hdl_parser.py, filter "_signal_clock" and "_signal_reset"
pseudo buses from component.xml files, append them as description
in the ports table, in the format
"{Bus} [...] is synchronous to this {domain}".
Also, adds collapsible directive

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00
Jorge Marques 58df312e8b docs: move guidelines, porting project main, repos git roles
Moves guidelines to user_guide as docs_guidelines.
Includes Porting HDL project user guide.
Replaces the Excel spreadsheet with raw space divided files.
Includes the 6 pinned at the org.
Contributors shall expand the list as needed.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00
Jorge Marques 468d02ea50 docs: update link roles, .gitignore
Update link roles to use the "text <link>" standard sphinx syntax.
Add __pycache__ and _build to .gitignore

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00
Jorge Marques cf056cf81c docs: add regmap directive
Automate table generation for register maps.
Based on tfcollins' vger python scripts.
There are docs/adi_regmap_*.txt with more than one regmap per file,
so the logic changed to allow that.
Using title tool as the unique identifier now.
It has a global option to set the default state (hidden or visible)
for the collpasible tables.
Also remove CSVs.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00
Jorge Marques 83d2bf9603 docs: automate parameters and interfaces tables
Uses Vivado generated components.xml files.
If the file is not found/generated, there is a fallback method.
Also, define bibliography per project, not globally.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00
Jorge Marques ef9c98f9b9 docs: Include sphinx documentation
The parameters directive allows to almost automatically generate the
parameters table.
It allows to add rich descriptions to the parameters, such as references,
while checking if they exist in the *_hw.tcl file a obtaining the types
and default values.
However, it cannot obtain parameters generated from a foreach loop yet,
making it incompatible with the axi_dmac_hw.tcl file for example.
This commit also joins the other extensions into a single adi_links
extension.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2023-09-27 14:36:34 -03:00